Method and device for detecting unreasonable component placement constraint

Abstract

The invention provides a method and a device for automatically detecting unreasonable RP constraints which are defined by a user, wherein the detection method comprises the following steps of: respectively producing a reference integrated circuit design and a user-defined integrated circuit design, wherein, in relation to the reference integrated circuit design, the user-defined integrated circuit design is added with component placement constraints which are defined by at least one user; then comparing the reference integrated circuit design with the user-defined integrated circuit design, and finding out all deviation paths of the user-defined integrated circuit design by means of a judgment standard in relation to the corresponding paths of the reference integrated circuit design; and then finding out all components which are defined by the component placement constraints defined by at least one user from the deviation paths, thereby finding out the unreasonable component placement constraints from the component placement constraints which are defined by at least one user. The method and the device for detecting unreasonable component placement constraints provided by the invention have the advantages that the detection result is accurate, the detection efficiency is high and the design results are more suitable to expected results.

Description

technical field [0001] The present invention relates to a method and device for detecting unreasonable constraints placed by users on component placement, and in particular to an automatic detection of user-defined unreasonable component placement in integrated circuit (integrated circuit, IC) design Method and apparatus for restraint. Background technique [0002] In IC design, usually according to the user's needs, the design tool will operate according to its default settings. Taking the placement of components as an example, the more common design methods are as follows: figure 1 shown. First, a gate-level netlist is generated in step 700 of a front-end design, and then the final IC is obtained through back-end design processes such as placement optimization step 701, clock tree establishment and optimization step 702, and connection optimization step 703. design results. This design method is simple and fast. However, in many cases, users think that the default desi...

AI Technical Summary

Problems solved by technology

But in fact, in many cases, the user-defined component placement constraints will not improve all of them, and there may even be some unreasonable constraints that lead to the deterioration of the design results.

However, the design tools in the industry have not provided the screening function for this part of user-defined constraints. Users can only judge whether unreasonable constraints have been added based on their own experience and check them out manually; thus it is difficult to guarantee ideal design results. and design efficiency

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