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Integrated non-linearity (INL) and differential non-linearity (DNL) correction techniques for digital-to-analog converters (DACs)

A digital-to-analog converter, integral nonlinear technology, applied in the direction of digital-to-analog converter, analog/digital conversion calibration/test, analog/digital conversion, etc.

Active Publication Date: 2011-05-18
INTERSIL INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

A challenge with this type of technique is that for any realistic value of N the LUT is typically enormous
Furthermore, INL optimization can result in DNL values ​​less than -1.0, resulting in a non-monotonic DAC, which is undesirable in control loop usage as described above

Method used

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  • Integrated non-linearity (INL) and differential non-linearity (DNL) correction techniques for digital-to-analog converters (DACs)
  • Integrated non-linearity (INL) and differential non-linearity (DNL) correction techniques for digital-to-analog converters (DACs)
  • Integrated non-linearity (INL) and differential non-linearity (DNL) correction techniques for digital-to-analog converters (DACs)

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Embodiment Construction

[0033] For INL correction, various techniques for reducing the effect of INL can be used, resulting in different trade-offs as they involve computational requirements and on-chip storage. As described in more detail below, in one embodiment, the most efficient segment of the DAC (e.g., figure 1 Each sub-segment of the middle segment 110_1) (except the end sub-segment, which is used to eliminate the unintentional gain error caused by INL correction) determines a correction code. Various correction techniques can be used including, but not limited to, zero-order correction (essentially INL offset correction), or first-order correction (linear fit between major inflection points in the INL curve).

[0034] Particular embodiments of the present invention relate to systems, devices, and methods that use a look-up table to reduce the INL of a DAC without modifying the DAC output voltage range, while still providing a monotonic DAC. In some embodiments, the size of the lookup table...

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Abstract

INL values are determined for a plurality of sub-segments of a DAC that is adapted to accept N bit digital input codes, and a first set of correction codes that can be used to reduce to a range of INL values (to thereby improve linearity of the DAC) are determined and stored. Additionally, DNL values are determined for the plurality of sub-segments for which INL values were determined, and a second set of correction codes that can be used to ensure that all values of DNL >-1 (to thereby ensure that the DAC is monotonic) are determined and stored. This can include using one or more extra bits of resolution to remap at least some of the 2 possible digital input codes (that can be accepted by the DAC) to more than 2 possible digital output codes, to ensure that all values of DNL >-1. Such stored first and second sets are thereafter used when performing digital to analog conversions.

Description

[0001] priority claim [0002] This application claims priority from the following U.S. patent applications: [0003] · Submitted by Iskender Agi on September 8, 2010 entitled "INTEGRATEDNON-LINEARITY (INL) AND DIFFERENTIAL NON-LINEARITY (DNL) CORRECTION TECHNIQUES" (Integrated Nonlinear (INL) and Differential Nonlinear (DNL) Correction Techniques) U.S. Patent Application No. 12 / 877,904 (Attorney Docket No. ELAN-01245US2); [0004] · Filed by Iskender Agi on November 12, 2009, entitled "OFFLINE LINEARITY CORRECTION TECHNIQUE FOR DIGITAL-TO-ANALOG CONVERTERS (DACS)" (Attorney Docket) U.S. Patent Application No. 61 / 260,801, No. ELAN-01245US0); and [0005] · Submitted by Iskender Agi on August 30, 2010, entitled "INL AND DNLCORRECTION TECHNIQUES FOR DIGITAL-TO-ANALOG CONVERTERS (DACS)" (INL and DNL Correction Techniques for Digital-to-Analog Converters (DACs)) (Proxy US Patent Application No. 61 / 378,321, Docket No. ELAN-01245US1), each of which is hereby incorporated by refere...

Claims

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Application Information

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IPC IPC(8): H03M1/10
CPCH03M1/1052H03M1/66
Inventor I·阿希
Owner INTERSIL INC
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