15 results about "Integral nonlinearity" patented technology

Phase interpolators are provided, the phase interpolators including: a first phase interpolator having a first output that outputs a first interpolated clock signal based on quadrature clock signals and a first phase interpolator control signal; a second phase interpolator having a second output that outputs a second interpolated clock signal based on the quadrature clock signals and a second phase interpolator control signal that is shifted from the first phase interpolator control signal by half of an integral nonlinearity (INL) period of the first phase interpolator; and a phase combiner that outputs a third interpolated clock signal based on the first interpolated clock signal and the second interpolated clock signal. In some of these embodiments, the phase interpolators further comprise a first amplitude limiter that receives the first interpolated clock signal and outputs a first amplitude-limited interpolated clock signal that is provided to the phase combiner.

The invention discloses a method and a system for improving resolution and linearity of a time sequence generator based on an FPGA (Field Programmable Gate Array), and belongs to the technical field of automatic test equipment. In order to solve the problem that an existing FPGA time sequence generator is difficult to consider high resolution, large dynamic range and high linearity at the same time, a multi-phase clock and coarse and fine delay lines of a carry chain are adopted to form a three-level time interpolation framework, and picosecond interpolation in the large dynamic range is achieved with extremely few logic resources; meanwhile, a time measurement channel is constructed in the chip to obtain actual physical delay, the actual physical delay is transmitted to the upper computer to execute a selection algorithm, and a target delay code with the minimum integral nonlinear error is screened out to update the delay code table. According to the invention, non-linear deviation caused by bottom hardware wiring is effectively overcome, the accuracy of time sequence edge placement and the system test rate are remarkably improved, and the method is mainly used for high-precision time sequence signal generation in digital integrated circuit automatic test equipment.

The application discloses a kind of FPGA-based timing generator resolution and linearity promotion method and system, belong to automatic test equipment technical field.For the problem that existing FPGA timing generator is difficult to consider high resolution, large dynamic range and high linearity, the application adopts multi-phase clock and carry chain coarse, fine delay line to form three-stage time interpolation architecture, to realize picosecond-level interpolation of large dynamic range with very few logic resources;At the same time, the actual physical delay is obtained by constructing a time measurement channel in the chip, and is transmitted to the host computer to execute the selection algorithm, and the target delay code with the smallest integral nonlinear error is selected to update the delay code table.The application effectively overcomes the nonlinear deviation caused by the underlying hardware wiring, significantly improves the accuracy of timing edge placement and the system test rate, and is mainly used for generating high-precision timing signals in digital integrated circuit automatic test equipment.

Circuitry for correcting phase interpolator rollover integral nonlinearity error includes rollover detector circuitry and correction circuitry. The rollover detector circuitry includes a forward rollover detector circuit for detecting when a forward rollover event of a phase interpolator occurs and a reverse rollover detector circuit for detecting when a reverse rollover event of the phase interpolator occurs. The correction circuitry adds a signed pre-distortion correction to a voltage controlled oscillator (VCO) clock period fractional value when the rollover detector circuitry has detected either a forward rollover event of the phase interpolator or a reverse rollover event of the phase interpolator.

Various example embodiments provide for handling phase interpolator (PI) integral non-linearity (INL) errors based on phase error measurements, which can be used in conjunction with clock data recovery (CDR) within a circuit, such as a data serializer / deserializer (SerDes) circuit. In particular, various example embodiments provide a PI system configured to measure and handle (e.g., reduce or correct) PI integral INL errors, where the PI system comprises a PI, a phase detector, a first-order path, a second-order loop, a phase integrator, a measurement component, and a look-up-table (LUT) component. For various example embodiments, the measurement component is configured to receive phase error information for an input data signal from the phase detector, receive frequency offset information from the second-order loop, receive phase position data for the input signal to the PI, and adjust mappings of one or more phase positions to the PI to reduce or correct non-linearity in the PI.

Provided is a method for measuring a DAC nonlinearity error based on a pseudo-random sequence. The method includes: numbering pseudo-random number values in a pseudo-random sequence to generate a serial number sequence; arranging the pseudo-random number values in the serial number sequence in a descending or ascending order to determine an order random array; sending the pseudo-random number values, as DAC code values, in the order random array to the DAC sequentially; determining a first differential voltage array and a second differential voltage array according to a voltage corresponding to the DAC code values and the DAC code values; and determining a nonlinearity error measurement result of the DAC according to a differential nonlinearity error test result of the DAC and an integral nonlinearity error test result of the DAC determined by the first differential voltage array and the second differential voltage array.

The application relates to an analog-to-digital converter testing system and method. A host computer sends a voltage output instruction to a power supply; when a first indication signal sent by the power supply is received, a sampling start instruction is sent to a device under test, and the first indication signal indicates that the output voltage of the power supply is stable. When it is determined that the device under test is in a sampling completion state, the host computer receives a code value obtained by sampling the output voltage by the device under test in response to the sampling start instruction; based on the code value, a preset analysis algorithm is used to generate a differential nonlinearity parameter and an integral nonlinearity error parameter, and performance detection of the device under test is completed. The application can realize that the device under test samples the established stable output voltage, reduces the code value jump problem when the device under test samples the unstable output voltage, and improves the test precision.

The application discloses a high-precision ADC linearity test method and system, comprising the following steps: inputting a plurality of signal differences to an ADC through a control signal generator, a voltage source, an operator and a channel of a multiplexer, and obtaining a group of output code bits of each signal difference; summing and subtracting two preset signal differences, and summing and subtracting the output code bits of the two preset signal differences, to obtain summing and subtracting results; determining a multivariate linear equation group according to a preset segmented nonlinear model containing a parameter to be solved, the summing and subtracting results and the output code bits; obtaining an optimal solution by solving the equation group, and determining integral nonlinear errors and differential nonlinear errors of the ADC according to the optimal solution and the preset segmented nonlinear model. The application can calculate common-mode and differential-mode of integral nonlinearity and differential nonlinearity, can reduce the precision requirement of an input signal, can greatly shorten test time and sampling points, and has simple system structure, fast algorithm running speed and wide application prospect.

A phase interpolator (PI) circuit (700) is described that generates an interpolated clock (PICLK) at a target phase in a phase range between two reference clocks to capture data in a capture circuit based on an interpolated code (S) within the interpolated code range. A clamp circuit (704) coupled to the PI circuit provides a reduced range of interpolated codes (S), where an integral nonlinearity (INL) of the interpolated clock is below a threshold such that interpolated clock-based data capture has a lower bit error rate, BER. As a result, an interpolation clock is generated within a reduced phase range corresponding to the reduced interpolation code range. When a target phase for the interpolated clock is outside a reduced phase range, the clamp circuit may adjust a target phase clock (PHAREF) relative to the reference clock to adjust the target phase to within the reduced phase range for improving the BER.

The invention relates to an ADC dynamic performance estimation method and device based on integral nonlinear data, and the method comprises the following steps: S1, obtaining the INL data of each transition level of an ADC; s2, a sinusoidal signal is set, and an INL data set with the same frequency as the sinusoidal signal is extracted from the INL data; and S3, performing spectral analysis and dynamic parameter calculation on the INL data set. An ADC dynamic performance estimation device based on integral nonlinear data comprises an INL data acquisition module, an INL data set extraction module and a spectrum analysis and dynamic parameter calculation module. The INL data acquisition module is used for acquiring INL data of each transition level of the ADC; the INL data set extraction module sets a sinusoidal signal and extracts an INL data set with the same frequency as the sinusoidal signal from INL data; and the spectrum analysis and dynamic parameter calculation module performs spectrum analysis and dynamic parameter calculation on the INL data set. Extra hardware is not needed, cost is reduced, and time is shortened.

The invention relates to the technical field of data compensation, in particular to a high-precision data compensation method and system. According to the technical scheme, the method comprises the following steps: data acquisition: synchronously acquiring target data and environment parameters, preprocessing the acquired original data to eliminate abnormal values and suppress random noise, and constructing a measurement matrix M and an environment matrix E; error modeling: calculating an integral nonlinear error INL and a differential nonlinear error DNL of the data based on the measurement matrix M, and establishing a nonlinear error fitting function fINL (x); and environment compensation: constructing an error equation containing the environment matrix E. Through organic combination of dynamic self-adaption, multi-source collaboration, intelligent learning and closed-loop control, a data compensation technology is upgraded from a static, isolated and passive traditional mode to a dynamic, collaborative and intelligent advanced mode, the compensation precision is extremely high, and the dynamic response speed and long-term environmental adaptability are excellent.

A phase interpolator (PI) for clock and data recovery (CDR) in a high-speed receiver implements nonlinearity mitigation. The PI interpolates between adjacent phase-shifted clock signals based on digital PI-codes to generate a sampling clock. To reduce phase nonlinearity at high frequencies, the PI applies zone-based dynamic biasing to phase interpolation elements. A bias generator selects and applies one or more bias values to PI unit cells based on a phase zone corresponding to the PI-code. The applied bias adjusts operating characteristics of the interpolation elements, such as bias current or transconductance, to reduce differential nonlinearity and integrated nonlinearity across the PI phase range. In some embodiments, PI unit cells are arranged in groups that receive independently selectable dynamic or fixed biases. The architecture improves phase linearity and timing alignment with low area and power overhead.

The application discloses a method and device for testing non-linearity of a high-speed serial interface chip, which hardly needs any testing equipment and has extremely low testing cost. The method comprises the following steps: providing a first local oscillation clock to a data source and a second local oscillation clock to a chip to be tested, wherein the first local oscillation clock and the second local oscillation clock have different frequencies; outputting a data signal from the data source to the chip to be tested, wherein the chip to be tested comprises a clock and data recovery circuit; sampling a control code generated by the chip to be tested after the clock and data recovery circuit is locked; calculating a statistical value of the control code and calculating differential non-linearity and integral non-linearity according to the statistical value.

The invention discloses a phase interpolator and related equipment, the phase interpolator comprises a load resistor and a phase interpolation module, the load resistor is used for controlling output common mode voltage; the phase interpolation module comprises N phase interpolation units, and the N phase interpolation units are connected in parallel; each phase interpolation unit comprises a first differential pair, a second differential pair, a control module and a current source module; the current source module is used for providing current flowing to the first differential pair and the second differential pair; and the control module is used for controlling current flowing to the first differential pair and the second differential pair respectively. The current flowing to the first differential pair and the second differential pair is more flexibly shunted through the control module, and the flexibility of input weight change between adjacent terms is improved, so that the integral nonlinear performance of the phase interpolator can be improved.

Embodiments of the present disclosure may comprise a system to determine integral nonlinearity of a device-under-test, the system comprising a measurement setup, with a voltage source to set a top voltage. Further the system comprises a multiplexer to selectively couple the set top voltage to the device-under-test or to selectively couple a bottom voltage to the device-under test. A processor is operable to record a plurality of measurements of the set top voltage and the bottom voltage and compute integral nonlinearity.