27 results about "Integral nonlinearity" patented technology

Some embodiments include apparatuses and methods using a clock generator to generate clock signals, the clock signals being out of phase with each other; a transmitting circuit to provide patterns of data at an output of the transmitting circuit responsive to timing of the clock signals; and calculation and control circuitry to calculate an integral nonlinearity vector that represents offsets of transitions of the patterns from respective target positions, and to generate control information based on the integral nonlinearity vector to adjust phases of the clock signals based on the control information.

A phase interpolator circuit has a first stage that selects a pair of phase vectors from among M available sets of pairs and a second stage that interpolates between the selected pair to phase align a sample clock. The interpolation functions applied to selected pairs of phase vectors can differ to account for integral non-linearity, duty-cycle distortion, phase errors, and crosstalk that vary between phase vectors.

Phase interpolators are provided, the phase interpolators including: a first phase interpolator having a first output that outputs a first interpolated clock signal based on quadrature clock signals and a first phase interpolator control signal; a second phase interpolator having a second output that outputs a second interpolated clock signal based on the quadrature clock signals and a second phase interpolator control signal that is shifted from the first phase interpolator control signal by half of an integral nonlinearity (INL) period of the first phase interpolator; and a phase combiner that outputs a third interpolated clock signal based on the first interpolated clock signal and the second interpolated clock signal. In some of these embodiments, the phase interpolators further comprise a first amplitude limiter that receives the first interpolated clock signal and outputs a first amplitude-limited interpolated clock signal that is provided to the phase combiner.

The invention discloses a method and a system for improving resolution and linearity of a time sequence generator based on an FPGA (Field Programmable Gate Array), and belongs to the technical field of automatic test equipment. In order to solve the problem that an existing FPGA time sequence generator is difficult to consider high resolution, large dynamic range and high linearity at the same time, a multi-phase clock and coarse and fine delay lines of a carry chain are adopted to form a three-level time interpolation framework, and picosecond interpolation in the large dynamic range is achieved with extremely few logic resources; meanwhile, a time measurement channel is constructed in the chip to obtain actual physical delay, the actual physical delay is transmitted to the upper computer to execute a selection algorithm, and a target delay code with the minimum integral nonlinear error is screened out to update the delay code table. According to the invention, non-linear deviation caused by bottom hardware wiring is effectively overcome, the accuracy of time sequence edge placement and the system test rate are remarkably improved, and the method is mainly used for high-precision time sequence signal generation in digital integrated circuit automatic test equipment.

The application discloses a kind of FPGA-based timing generator resolution and linearity promotion method and system, belong to automatic test equipment technical field.For the problem that existing FPGA timing generator is difficult to consider high resolution, large dynamic range and high linearity, the application adopts multi-phase clock and carry chain coarse, fine delay line to form three-stage time interpolation architecture, to realize picosecond-level interpolation of large dynamic range with very few logic resources;At the same time, the actual physical delay is obtained by constructing a time measurement channel in the chip, and is transmitted to the host computer to execute the selection algorithm, and the target delay code with the smallest integral nonlinear error is selected to update the delay code table.The application effectively overcomes the nonlinear deviation caused by the underlying hardware wiring, significantly improves the accuracy of timing edge placement and the system test rate, and is mainly used for generating high-precision timing signals in digital integrated circuit automatic test equipment.

The invention relates to a calibration method for integral nonlinearity of an analog-to-digital converter of a standard meter and the analog-to-digital converter, and belongs to the field of calibration of analog-to-digital converters. The method comprises the following steps: firstly, dividing a voltage range of an analog-to-digital converter to be calibrated into a plurality of calibration intervals at least comprising two corresponding voltage values; inputting an analog quantity signal corresponding to the voltage value in each calibration interval into the analog-to-digital converter to be calibrated to obtain a corresponding measurement code value; and finally, according to the two measurement code values randomly selected in each calibration interval, the two ideal code values and the linear relationship between the measurement code values and the ideal code values, obtaining a calibration coefficient and an offset for performing integral nonlinear error correction in each calibration interval. The analog-to-digital converter to be calibrated is calibrated section by section, the correction precision is high, the calculated amount is smaller, and full-scale coverage is achieved.

The embodiment of the invention provides an analog-to-digital conversion circuit, a chip and electronic equipment, and the analog-to-digital conversion circuit comprises a comparison processing module, a switched capacitor module and a switch control module. A comparison processing module outputs a digital signal according to a comparison result of a first generation voltage and a second generation voltage and generates a feedback signal based on the digital signal, a switched capacitor module determines the first generation voltage and the second generation voltage according to a control signal, and a switch control module generates a control signal according to the feedback signal. The switching quantity of unit capacitors in the switched capacitor module is gradually reduced in each quantization stage, and the switching quantity of the unit capacitors is remarkably reduced along with the increase of the switching times in the quantization stage, so that the switching power consumption of the unit capacitors is reduced, and the precision loss caused by capacity mismatch of the unit capacitors is reduced; therefore, the precision of analog-to-digital conversion is improved, and nonlinear indexes such as differential nonlinearity and integral nonlinearity are improved.

A phase-interpolator (PI) circuit generates an interpolated clock to capture data in a capture circuit at a target phase in a phase range between two reference clocks based on an interpolation code within a range of interpolation codes is described. A clamping circuit coupled to the PI circuit provides an interpolation code within a reduced range, where the integral non-linearity (INL) of the interpolated clocks is below a threshold, such that data capture based on the interpolated clock has a lower bit error rate (BER). As a result, the interpolated clock is generated within a reduced phase range corresponding to the reduced range of interpolation codes. When a target phase for an interpolated clock is outside the reduced phase range, the clamping circuit may adjust the target phase clock relative to a reference clock to adjust the target phase to be within the reduced phase range for improved BER.

Circuitry for correcting phase interpolator rollover integral nonlinearity error includes rollover detector circuitry and correction circuitry. The rollover detector circuitry includes a forward rollover detector circuit for detecting when a forward rollover event of a phase interpolator occurs and a reverse rollover detector circuit for detecting when a reverse rollover event of the phase interpolator occurs. The correction circuitry adds a signed pre-distortion correction to a voltage controlled oscillator (VCO) clock period fractional value when the rollover detector circuitry has detected either a forward rollover event of the phase interpolator or a reverse rollover event of the phase interpolator.

Provided is a method for measuring a DAC nonlinearity error based on a pseudo-random sequence. The method includes: numbering pseudo-random number values in a pseudo-random sequence to generate a serial number sequence; arranging the pseudo-random number values in the serial number sequence in a descending or ascending order to determine an order random array; sending the pseudo-random number values, as DAC code values, in the order random array to the DAC sequentially; determining a first differential voltage array and a second differential voltage array according to a voltage corresponding to the DAC code values and the DAC code values; and determining a nonlinearity error measurement result of the DAC according to a differential nonlinearity error test result of the DAC and an integral nonlinearity error test result of the DAC determined by the first differential voltage array and the second differential voltage array.

[Task] To provide a weighting information generating device that can generate weighting information to improve integral nonlinearity without using a high-precision digital-to-analog converter. [Solution] A weighting information generating device 20 includes voltage input units 21, 22, 23, 24 equipped with voltage generating units 21, 22 that generate a predetermined binary voltage, and voltage offset units 21, 23 that zero-shift the binary voltage generated by the voltage generating units 21, 22 by multiplying it by an offset voltage, and a binary voltage that is stepwise zero-shifted per given voltage is sequentially input to an analog-to-digital converter 10, and an information generating unit 21 that acquires an output value corresponding to the binary voltage output from the analog-to-digital converter 10 and generates weighting information based on the acquired output value.

Various example embodiments provide for handling phase interpolator (PI) integral non-linearity (INL) errors based on phase error measurements, which can be used in conjunction with clock data recovery (CDR) within a circuit, such as a data serializer / deserializer (SerDes) circuit. In particular, various example embodiments provide a PI system configured to measure and handle (e.g., reduce or correct) PI integral INL errors, where the PI system comprises a PI, a phase detector, a first-order path, a second-order loop, a phase integrator, a measurement component, and a look-up-table (LUT) component. For various example embodiments, the measurement component is configured to receive phase error information for an input data signal from the phase detector, receive frequency offset information from the second-order loop, receive phase position data for the input signal to the PI, and adjust mappings of one or more phase positions to the PI to reduce or correct non-linearity in the PI.

The present disclosure relates to INL detection and calibration for phase interpolators. An apparatus includes control logic coupled to a phase detector circuit and an adjustable delay circuit. The control logic is configured to obtain a state of a first phase of an output signal of a phase interpolator relative to a second phase of a reference signal, and adjust a delay of the reference signal until the second phase matches the first phase. The control logic is further configured to measure a total delay of the reference signal when the second phase matches the first phase, and determine an integral nonlinearity of the phase interpolator at a first code based on the total delay. The control logic can further calibrate the first code of the phase interpolator based at least in part on the integral nonlinearity.

The present invention is a method for realizing an automatic test system for an axis-angle chip, in the field of chip automatic test. The method is based on the interface control software developed on the LabView platform, and cooperates with the embedded control software developed on the Keil platform to complete parameter setting, operation control and data acquisition for test and measurement equipment and instruments, realize the communication, data exchange and command control between the computer and the main control board, complete the automatic test process, and realize the test of the voltage and current of the axis-angle chip, the angle conversion accuracy and the integral nonlinear error, the speed accuracy and the maximum tracking speed, the reference signal frequency, the reference center voltage and the DC mismatch, the reference voltage and the AC mismatch, the reference voltage and the reference voltage suppression, and the logic output high level and low level function. The method of the present invention can effectively replace the manual test of the corresponding parameters of the chip, and at the same time improve the test efficiency of the single-chip chip and the reliability of the test data.

Provided is a method for measuring a DAC nonlinearity error based on a pseudo-random sequence. The method includes: numbering pseudo-random number values in a pseudo-random sequence to generate a serial number sequence; arranging the pseudo-random number values in the serial number sequence in a descending or ascending order to determine an order random array; sending the pseudo-random number values, as DAC code values, in the order random array to the DAC sequentially; determining a first differential voltage array and a second differential voltage array according to a voltage corresponding to the DAC code values and the DAC code values; and determining a nonlinearity error measurement result of the DAC according to a differential nonlinearity error test result of the DAC and an integral nonlinearity error test result of the DAC determined by the first differential voltage array and the second differential voltage array.

The application relates to an analog-to-digital converter testing system and method. A host computer sends a voltage output instruction to a power supply; when a first indication signal sent by the power supply is received, a sampling start instruction is sent to a device under test, and the first indication signal indicates that the output voltage of the power supply is stable. When it is determined that the device under test is in a sampling completion state, the host computer receives a code value obtained by sampling the output voltage by the device under test in response to the sampling start instruction; based on the code value, a preset analysis algorithm is used to generate a differential nonlinearity parameter and an integral nonlinearity error parameter, and performance detection of the device under test is completed. The application can realize that the device under test samples the established stable output voltage, reduces the code value jump problem when the device under test samples the unstable output voltage, and improves the test precision.

A system and method for compensating segmented DAC intrinsic INL by adjusting the relative strength of DAC thermometer segments. In the method, the strength of each thermometer segment is adjusted sequentially to reduce INL to 0 at one point on each thermometer code range. The strength of the binary section is also adjusted to further reduce INL while conserving output amplitude. The system includes a calibration circuit that senses the DAC differential output and compares it to an ideal output generated from the same DAC via dithering between 0 and a maximum code. The compensation scheme only performs a specific type of DAC compensation, specifically compensating for systematic non-linearity rather than for mismatch-induced non-linearity. The method can also be applied to calibrate a full thermometer DAC.

The application discloses a high-precision ADC linearity test method and system, comprising the following steps: inputting a plurality of signal differences to an ADC through a control signal generator, a voltage source, an operator and a channel of a multiplexer, and obtaining a group of output code bits of each signal difference; summing and subtracting two preset signal differences, and summing and subtracting the output code bits of the two preset signal differences, to obtain summing and subtracting results; determining a multivariate linear equation group according to a preset segmented nonlinear model containing a parameter to be solved, the summing and subtracting results and the output code bits; obtaining an optimal solution by solving the equation group, and determining integral nonlinear errors and differential nonlinear errors of the ADC according to the optimal solution and the preset segmented nonlinear model. The application can calculate common-mode and differential-mode of integral nonlinearity and differential nonlinearity, can reduce the precision requirement of an input signal, can greatly shorten test time and sampling points, and has simple system structure, fast algorithm running speed and wide application prospect.

A phase interpolator (PI) circuit (700) is described that generates an interpolated clock (PICLK) at a target phase in a phase range between two reference clocks to capture data in a capture circuit based on an interpolated code (S) within the interpolated code range. A clamp circuit (704) coupled to the PI circuit provides a reduced range of interpolated codes (S), where an integral nonlinearity (INL) of the interpolated clock is below a threshold such that interpolated clock-based data capture has a lower bit error rate, BER. As a result, an interpolation clock is generated within a reduced phase range corresponding to the reduced interpolation code range. When a target phase for the interpolated clock is outside a reduced phase range, the clamp circuit may adjust a target phase clock (PHAREF) relative to the reference clock to adjust the target phase to within the reduced phase range for improving the BER.

The invention relates to an ADC dynamic performance estimation method and device based on integral nonlinear data, and the method comprises the following steps: S1, obtaining the INL data of each transition level of an ADC; s2, a sinusoidal signal is set, and an INL data set with the same frequency as the sinusoidal signal is extracted from the INL data; and S3, performing spectral analysis and dynamic parameter calculation on the INL data set. An ADC dynamic performance estimation device based on integral nonlinear data comprises an INL data acquisition module, an INL data set extraction module and a spectrum analysis and dynamic parameter calculation module. The INL data acquisition module is used for acquiring INL data of each transition level of the ADC; the INL data set extraction module sets a sinusoidal signal and extracts an INL data set with the same frequency as the sinusoidal signal from INL data; and the spectrum analysis and dynamic parameter calculation module performs spectrum analysis and dynamic parameter calculation on the INL data set. Extra hardware is not needed, cost is reduced, and time is shortened.

The invention relates to the technical field of data compensation, in particular to a high-precision data compensation method and system. According to the technical scheme, the method comprises the following steps: data acquisition: synchronously acquiring target data and environment parameters, preprocessing the acquired original data to eliminate abnormal values and suppress random noise, and constructing a measurement matrix M and an environment matrix E; error modeling: calculating an integral nonlinear error INL and a differential nonlinear error DNL of the data based on the measurement matrix M, and establishing a nonlinear error fitting function fINL (x); and environment compensation: constructing an error equation containing the environment matrix E. Through organic combination of dynamic self-adaption, multi-source collaboration, intelligent learning and closed-loop control, a data compensation technology is upgraded from a static, isolated and passive traditional mode to a dynamic, collaborative and intelligent advanced mode, the compensation precision is extremely high, and the dynamic response speed and long-term environmental adaptability are excellent.

A phase interpolator (PI) for clock and data recovery (CDR) in a high-speed receiver implements nonlinearity mitigation. The PI interpolates between adjacent phase-shifted clock signals based on digital PI-codes to generate a sampling clock. To reduce phase nonlinearity at high frequencies, the PI applies zone-based dynamic biasing to phase interpolation elements. A bias generator selects and applies one or more bias values to PI unit cells based on a phase zone corresponding to the PI-code. The applied bias adjusts operating characteristics of the interpolation elements, such as bias current or transconductance, to reduce differential nonlinearity and integrated nonlinearity across the PI phase range. In some embodiments, PI unit cells are arranged in groups that receive independently selectable dynamic or fixed biases. The architecture improves phase linearity and timing alignment with low area and power overhead.

The application discloses a method and device for testing non-linearity of a high-speed serial interface chip, which hardly needs any testing equipment and has extremely low testing cost. The method comprises the following steps: providing a first local oscillation clock to a data source and a second local oscillation clock to a chip to be tested, wherein the first local oscillation clock and the second local oscillation clock have different frequencies; outputting a data signal from the data source to the chip to be tested, wherein the chip to be tested comprises a clock and data recovery circuit; sampling a control code generated by the chip to be tested after the clock and data recovery circuit is locked; calculating a statistical value of the control code and calculating differential non-linearity and integral non-linearity according to the statistical value.

The present invention relates to a high-speed and high-precision slope generation module for CMOS image sensors, belonging to the field of CMOS image sensors; comprising 2 N +2 M A current steering unit, a unidirectional ramp control module, a resistor Rload, a resistor Rdummy, and a capacitor Cfilter; wherein the unidirectional ramp control module is provided with 2 N +2 M A control signal output terminal, each output terminal is respectively connected to two input terminals of a corresponding current steering unit; one output terminal of each current steering unit is connected to a resistor Rdummy and then grounded, and the other output terminal is connected to a ramp reference voltage output point Vout; the ramp reference voltage output point Vout is respectively connected in parallel with a resistor Rload and a capacitor Cfilter; a step-shaped signal is filtered to generate a ramp; the present invention can eliminate the glitch voltage of the output point, thereby improving the noise, differential nonlinearity, and integral nonlinearity performance of the overall readout circuit, and can reduce the slope deviation between different chips.

A detection method for an N-bit analog-to-digital converter, the detection method comprising: selecting continuous M bits to be measured according to the static integral nonlinearity error requirement of the N-bit analog-to-digital converter to be measured, wherein at least one of the M bits to be measured is a non-exact bit, and determining a determination condition for the integral nonlinearity error of the M bits to be measured, where M and N are positive integers, and M < N; performing an integral nonlinearity error test on the M bits to be measured; in response to the measured integral nonlinearity error satisfying the determination condition, confirming that the N-bit analog-to-digital converter is qualified, and in response to the measured integral nonlinearity error not satisfying the determination condition, confirming that the N-bit analog-to-digital converter is unqualified.

The invention discloses a phase interpolator and related equipment, the phase interpolator comprises a load resistor and a phase interpolation module, the load resistor is used for controlling output common mode voltage; the phase interpolation module comprises N phase interpolation units, and the N phase interpolation units are connected in parallel; each phase interpolation unit comprises a first differential pair, a second differential pair, a control module and a current source module; the current source module is used for providing current flowing to the first differential pair and the second differential pair; and the control module is used for controlling current flowing to the first differential pair and the second differential pair respectively. The current flowing to the first differential pair and the second differential pair is more flexibly shunted through the control module, and the flexibility of input weight change between adjacent terms is improved, so that the integral nonlinear performance of the phase interpolator can be improved.

Embodiments of the present disclosure may comprise a system to determine integral nonlinearity of a device-under-test, the system comprising a measurement setup, with a voltage source to set a top voltage. Further the system comprises a multiplexer to selectively couple the set top voltage to the device-under-test or to selectively couple a bottom voltage to the device-under test. A processor is operable to record a plurality of measurements of the set top voltage and the bottom voltage and compute integral nonlinearity.