Multiphase clock generation circuit

Abstract

The invention discloses a multiphase clock generation circuit, and belongs to the technical field of electronics. The multiphase clock generation circuit comprises a delay chain, a phase discriminator, a counter and a lookup table module. The phase discriminator judges whether delay of the delay chain is equal to a reference clock period or not, and the delay of delay units of the delay chain is adjusted according to output results of the phase discriminator, so that the delay of the delay chain is equal to the reference clock period. In the adjusting process and N delay units, the delay of k delay units is smaller than an ideal value, the delay of N-k delay units is larger than the ideal value, and both N and k are integers. The delay units are divided into 2*min [k, (N-k)] +1 groups, and the difference of control codes of the delay units in adjacent groups is 1, so that an optimized linearity result is obtained. The multiphase clock generation circuit has the advantages of simple structure, high reliability, low differential nonlinearity and integral nonlinearity and the like.

Description

technical field [0001] The invention belongs to the field of electronic technology and relates to a clock generation circuit, in particular to a clock generation circuit capable of generating a plurality of clock outputs with uniform phase difference distribution under the excitation of a fixed-frequency reference clock. Background technique [0002] With the continuous improvement of VLSI processing technology, SoC chips contain more and more transistors. In a SoC designed with synchronous digital circuits, the synchronous clock usually has to drive a large number of transistors and interconnection lines to reach the functional modules connected to it in different positions, so that the delay of the clock reaching the functional modules in different positions in the circuit is inconsistent, which may cause As a result, the clock cannot ensure that all functional modules work synchronously, resulting in circuit logic errors. Therefore, the generation and distribution of on-c...

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Problems solved by technology

[0023] It can be seen that when r=N / 2, the maximum integral nonlinearity is T step ×N / 4, and the large integral nonlinearity affects the uniformity of the output clock phase, which in turn affects the subsequent circuit accuracy

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