A multi-phase clock generation circuit

Abstract

A multi-phase clock generation circuit belongs to the field of electronic technology. It consists of delay chain, phase detector, counter and look-up table modules. The invention uses a phase detector to judge whether the delay of the delay chain is equal to the reference clock cycle, and adjusts the delay of each delay unit of the delay chain according to the output result of the phase detector, so that the delay of the delay chain is equal to the reference clock cycle. At the same time, in the adjustment process, among the N delay units, the delay of k delay units is less than the ideal value, and the delay of N-k delay units is greater than the ideal value. N and k are both integers. By designing the look-up table, the delay units are divided into 2×min[k,(N-k)]+1 groups, and the control codes of the delay units in adjacent groups differ by 1, so that the optimal linearity result is obtained. The invention has the advantages of simple structure, high reliability, low differential nonlinearity and integral nonlinearity, and the like.

Description

technical field [0001] The invention belongs to the field of electronic technology and relates to a clock generation circuit, in particular to a clock generation circuit capable of generating a plurality of clock outputs with uniform phase difference distribution under the excitation of a fixed-frequency reference clock. Background technique [0002] With the continuous improvement of VLSI processing technology, SoC chips contain more and more transistors. In a SoC designed with synchronous digital circuits, the synchronous clock usually has to drive a large number of transistors and interconnection lines to reach the functional modules connected to it in different positions, so that the delay of the clock reaching the functional modules in different positions in the circuit is inconsistent, which may cause As a result, the clock cannot ensure that all functional modules work synchronously, resulting in circuit logic errors. Therefore, the generation and distribution of on-c...

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Problems solved by technology

[0023] It can be seen that when r=N / 2, the maximum integral nonlinearity is T step ×N / 4, and the large integral nonlinearity affects the uniformity of the output clock phase, which in turn affects the subsequent circuit accuracy

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