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Data size-based shuffle switch matrix compression method

A switching matrix and data granularity technology, applied in machine execution devices, concurrent instruction execution, etc., can solve the problems of large complex operation ratio and data granularity difference, and achieve the effect of compressing capacity, reducing power consumption, and improving utilization rate

Active Publication Date: 2011-05-25
NAT UNIV OF DEFENSE TECH
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Problems solved by technology

[0008] Programs of different applications (or different program segments of the same application) often have different data widths. For example, in video algorithms, data widths are mostly bytes or halfwords. In wireless communication algorithms, complex operations (data widths of word or double word) accounted for a large proportion, the above-mentioned phenomenon has also caused the data granularity of the shuffling request of different programs (or different program segments of the same application program) to also have a large difference, which seeks more efficient for the present invention The switch matrix compression method offers the possibility of

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  • Data size-based shuffle switch matrix compression method
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  • Data size-based shuffle switch matrix compression method

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[0040] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0041] In the preprocessing stage of the present invention, for each shuffling request, the final shuffling data granularity is determined step by step, and the switch matrix is ​​compressed according to the data granularity determined step by step, and finally further compressed according to the current granularity index method, so that Complete the final compression of the switch matrix.

[0042]Assume that the total width of the data path of the processor is W bits, the minimum data granularity is G bits, the size of the Crossbar is N*N, and the width of each port is G bits (where W and G are integer powers of 2, And N=W / G), then the shuffling mode of each shuffling request is initially an N*N switch matrix, set it as X, and the value of each element is X i,j (1≤i≤N-1, 1≤j≤N-1), assuming that the maximum data granularity supported...

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Abstract

The invention discloses a data size-based shuffle switch matrix compression method, which comprises the following steps of: step 1, when performing data size-based shuffle switch matrix compression according to a shuffle request, setting the data size of the current shuffle request to be the smallest data size first; step 2, judging whether the data size of the current shuffle request can be doubled, and if the data size of the current shuffle request cannot be doubled, skipping to the step 3, otherwise, skipping to the step 4; step 3, doubling the current data size, compressing the current shuffle switch matrix according to the doubled data size, and skipping to the step 2; step 4, further compressing the current switch matrix by using the current size indexing method; and step 5, judging whether the current shuffle request is the last shuffle request in the procedure, if the current shuffle request is not the last shuffle request, processing the next shuffle request, and skipping tothe step 1, otherwise, ending the algorithm. The data size-based shuffle switch matrix compression method is simple in principle, is easy and convenient to operate, and can effectively improve the utilization ratio and the compression efficiency of a shuffle mode memory.

Description

technical field [0001] The present invention mainly relates to the field of a general-purpose processor or a digital signal processor (Digital Signal Processor, DSP) adopting Single Instruction Stream Multiple Data Streams (Single Instruction stream Multiple Data streams, SIMD) technology, in particular to a kind of application in SIMD or DSP The shuffled switch matrix compression method. Background technique [0002] SIMD technology, represented by subword parallel and vector technology, has great advantages in solving data-intensive applications such as media processing and wireless communication, so it has been widely used and developed, and is favored by processors, especially DSP. . The shuffling unit is mainly responsible for the data interaction between the registers of each processing unit of the SIMD component, and is a key component that restricts the performance of parallel processing units. [0003] The main structure of the hardware of the shuffling unit gener...

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Application Information

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IPC IPC(8): G06F9/38
Inventor 陈书明刘胜万江华陈海燕陈跃跃孙海燕张凯王耀华刘祥远李振涛
Owner NAT UNIV OF DEFENSE TECH
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