Electric test structure and method for measuring epitaxial graphic offset

Abstract

The invention relates to an electric test structure for measuring epitaxial graphic offset, comprising a buried layer formed on the surface of a semiconductor substrate, an epitaxial layer formed on the surface of the semiconductor substrate, a plug region equidistantly which is formed in the epitaxial layer on the surface of the semiconductor substrate and has a preset offset different with the buried layer along the same direction, a contact hole formed on the surface of the plug region as well as a first conductive connection, a second conductive connection and a third conductive connection which are sequentially formed at the contact hole on the adjacent plug region. The method for measuring the epitaxial graphic offset comprises the step of respectively carrying out an electric test on the electric test structure with different preset offsets. In the invention, the electric test structure is utilized to measure the epitaxial graphic offset, not only is the measuring accuracy higher, but also the registration error of a graph after extension to the graph before extension can be effective reduced.

Description

technical field [0001] The invention relates to an epitaxy process in the manufacture of integrated circuits, in particular to an electrical test structure and method for measuring the offset of epitaxy patterns. Background technique [0002] In the bipolar semiconductor manufacturing process, the method of growing a single crystal semiconductor thin film on the surface of a silicon substrate is called epitaxy. There are many benefits to epitaxial growth on the initial wafer. For one, the epitaxial layer does not need to have the same doping type as the underlying wafer. For example, in a bipolar process, an N-type epitaxial layer can be grown on a P-type substrate. Second, unlike CZ silicon, epitaxial silicon is not contaminated by oxygen or carbon elements. [0003] At the same time, a buried layer is also allowed to be formed in the epitaxial layer. The N+ buried layer becomes a critical step in most bipolar processes because it enables the fabrication of vertical NPN...

AI Technical Summary

Problems solved by technology

[0007] The present invention aims at defects such as the inaccurate compensation of the offset of the epitaxial pattern in the prior art and the inability to effectively control the registration error of the post-extended pattern and the pre-extended pattern, and provides an electrical test for measuring the offset of the epitaxial pattern structure

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