Clock synchronization device and method
A clock synchronization and master clock technology, applied in the field of data communication, can solve problems such as heavy burden, affecting time synchronization accuracy, and affecting recovery accuracy
Inactive Publication Date: 2015-01-28
ZTE CORP +1
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Problems solved by technology
[0005] In the related art, the solution of implementing PTP 1588 is realized by software except for extracting and modifying the time stamp by hardware, such as using CPU software to manage PTP messages. A large number of ports are overloaded (especially when the frequency recovery requires a high frequency of PTP packets, otherwise the recovery accuracy will be affected), therefore, using CPU software to maintain PTP packets will cause a heavy CPU load and affect the time synchronization accuracy.
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[0027] Hereinafter, the present invention will be described in detail with reference to the drawings and examples. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.
[0028] In this embodiment, a clock synchronization device is provided, which is used to realize the precise clock synchronization protocol PTP1588 through hardware, figure 1 is a structural block diagram of a clock synchronization device according to an embodiment of the present invention, such as figure 1 As shown, the device includes: a time processing module 10, an identification module 12, a separation module 14, a protocol processor 16 and a CPU processing module 18, and the structure will be described below.
[0029] The time processing module 10 is used for sampling and generating and / or modifying the time stamp of the message of PTP 1588 according to the time information obtained by sampling...
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The invention discloses a clock synchronization device and method. The device realizes a precision clock synchronization protocol PTP 1588 by adopting hardware and comprises a time processing module, a recognizing module, a separating module, a protocol processor and a CPU (Central Processing Unit) processing module, wherein the time processing module is used for sampling and generating and / or correcting a timestamp of a message of PTP1588 according to sampled time information; the recognizing module is connected to the time processing module and used for correcting the message received by the time processing module by using an asymmetric compensation value and a path delay value; the separating module is connected to the recognizing module and used for carrying out path processing on the received message according to a working mode of a time synchronization device; the protocol processor is connected to the separating module and used for obtaining the type of the received message and processing the received message in a type corresponding way; and the CPU processing module is used for selecting a master clock by using an optimal master clock algorithm and / or calculating a master-slave time difference and carrying out time synchronization. By adopting the invention, the time and frequency restoring precision is improved.
Description
technical field [0001] The present invention relates to the field of data communication, in particular, to a clock synchronization device and method. Background technique [0002] Packet Transport Network (abbreviated as PTN) can realize high-efficiency transmission of packet services, among which, PTN can not only transmit data such as Ethernet, Generalized Multi Protocol Label Switching (Generalized Multi Protocol Label Switching, abbreviated as GMPLS), etc. Time Division Multiplex (TDM for short) data is transmitted. [0003] The synchronization of the clock by the PTN is mainly reflected in two aspects: first, when carrying TDM services or intercommunicating with the Public Switched Telephone Network (PSTN for short), it is necessary to provide a synchronization function at the TDM interface; Second, when the PTN network carries 3G base station services, for example, time division synchronous code division multiple access (Time Division-synchronous Code Division Multipl...
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IPC IPC(8): H04L7/00H04J3/06
Inventor 张小卫徐健
Owner ZTE CORP