Grid drive circuit unit and grid drive circuit

Abstract

The invention discloses a grid drive circuit unit, comprising a signal input interface, receiving an input pulse signal; a signal output interface, outputting a grid drive signal; a first transistor, sending the input pulse signal to a control electrode of a second transistor, under the control of a first clock signal; and a second transistor, sending a second clock signal to the signal output interface, in a state of being turned on. Further, when the first clock signal and the input pulse signal are of high level, cut-in voltage is provided to the second transistor; when the first clock signal is of the high level and the input signal is of low level, potential of the control electrode of the second transistor is pulled down, to turn the second transistor off; when the second clock signal is changed to be of high level, the grid drive signal is outputted by the signal output interface and when the second clock signal is of the low level, the signal output interface voltage is pulleddown. The first clock signal and the second clock signal have the same period and duty ratio, and the high level of the first clock signal comes before the high level of the second clock signal. The grid drive circuit unit can reduce the area of the grid drive circuit.

Description

technical field [0001] The invention relates to the field of electronics, in particular to a gate drive circuit unit and a gate drive circuit of a panel device. Background technique [0002] The gate drive circuit is one of the important components of the flat panel display. In recent years, integrated gate drive circuits have become a hot research topic in flat panel display technology. The so-called integrated gate drive circuit means that the gate drive circuit is composed of thin-film transistors (TFTs), and the gate drive circuit is manufactured simultaneously with the pixel TFTs in the panel and formed on the display substrate. [0003] The integrated design of the gate drive circuit can not only reduce the number of peripheral gate drive chips and the pressing and sealing process of the drive chips, but also reduce the quality and thickness of the panel, narrow the frame of the panel and make the appearance more beautiful, making the The overall cost of the display ...

AI Technical Summary

Problems solved by technology

However, amorphous silicon TFT has the problems of low carrier mobility and threshold voltage drift. Therefore, it is generally necessary to use a bootstrap method to improve the driving capability of the TFT, and use a half-cycle bias to suppress the threshold voltage drift of the pull-down TFT.

In addition, the current amorphous silicon TFT process is non-self-aligned, and the parasitic capacitance is large, which brings a more significant clock feed through effect (clock feed through effect)

[0005] In the previously reported gate drive circuit scheme, in order to suppress the clock feedthrough effect, the number of transistors in the circuit unit reaches ten or more, not only the number of total devices is large, the connection is complicated, the layout area is large, and the yield is also low.

E.g, figure 1 What is shown is a gate drive circuit unit disclosed by Seung-hwan Moon et al. (US Patent No. 7486269). The gate drive circuit unit uses nine transistors and one capacitor. The circuit connection is complicated and the layout area is large.

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