Apparatus and method for generating a waveform test signal having crest factor emulation of random jitter

Abstract

A signal generating device has a display and a central processing unit for setting parameters for a serial data pattern and parameters for deterministic and random jitter impairments, and a displacement crest factor emulation impairment to be applied to the serial data pattern. A waveform record file is generated using the serial data pattern parameters, the impairment parameters for the deterministic jitter and random jitter, and the displacement crest factor emulation impairment. The displacement crest factor emulation impairment is selectively positioned in the impaired serial data pattern. A waveform generation circuit receives the waveform record file and generates an impaired serial data pattern analog output signal based on the serial data pattern, deterministic and random jitter impairments, and the displacement crest factor emulation impairment with the displacement crest factor emulation impairment being selectively positioned in the impaired serial data pattern analog output signal.

Description

Background technique [0001] In a high speed serial system (HHS), one performance measure of a receiver is the bit error rate or bit error rate. The bit error rate performance of a receiver will depend on the total jitter in the received signal, which is a combination of both deterministic and random jitter. Jitter has a significant impact on the bit error rate in HSS systems, exceeding the rate of gigabits per second. Generally, a transmitter in an HHS system outputs a differential signal that is coupled to a receiver via a cable and backplane. The differential signal is coupled to an equalizer that includes a comparator that converts the differential signal into a single-ended signal. The single-ended signal is coupled to a clock recovery circuit that crafts a data rate clock signal based on the timing of the incoming waveform logic transitions. The resulting clock includes low frequency jitter on the data. The recovered clock sets the timing of the decision circuit that ...

AI Technical Summary

Problems solved by technology

If the setup and hold times are greater than the distance between the two points 10 and 12, the receiver will -12 bit error rate operation, and the test fails

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