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Method and device for implementing interlacing or deinterlacing

A deinterleaving and matrix technology, applied in the field of data transmission, can solve the problems of large storage overhead and large processing delay, and achieve the effects of improving processing functions, reducing processing delay, and saving storage space

Active Publication Date: 2011-09-28
ZTE CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] This kind of interleaving and deinterleaving method needs to cache all the data in the matrix, so it has the disadvantages of large storage overhead and large processing delay

Method used

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  • Method and device for implementing interlacing or deinterlacing
  • Method and device for implementing interlacing or deinterlacing
  • Method and device for implementing interlacing or deinterlacing

Examples

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Embodiment Construction

[0027] The basic idea of ​​the present invention is to cache the original data to be interleaved or to be deinterleaved into the pre-processing cache unit; to calculate the correction factor table in conjunction with the dummy element to calculate the read-write control address; according to the read-write control address, read from the pre-process cache unit The original data to be interleaved or deinterleaved is taken, and the processed buffer unit is written to complete the interleaving or deinterleaving operation.

[0028] The technical solutions of the present invention will be further elaborated below in conjunction with the accompanying drawings and specific embodiments.

[0029] figure 1 It is a schematic flow chart of an implementation method of interleaving or deinterleaving in the present invention, such as figure 1 As shown, the method includes:

[0030] Step 101, buffering the original data to be interleaved or to be deinterleaved into the pre-processing buffer ...

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PUM

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Abstract

The invention discloses a method for implementing interlacing or deinterlacing. The method comprises the following steps: caching original data to be interlaced or deinterlaced into a pre-treatment cache unit; combining with dummy computing modifying factors to compute a read-write control address; and according to the read-write control address, reading the original data to be interlaced or deinterlaced in the pre-treatment cache unit and writing in the pre-treatment cache unit to finish interlacing or deinterlacing operation. The invention also discloses a device for implementing interlacing or deinterlacing. By using the method and the device, data to be treated are not required to be subjected to matrix cache in the interlacing or deinterlacing process, thus saving the storage space and reducing the time delay in the treatment.

Description

technical field [0001] The invention relates to the data transmission technology in the third generation partnership project long-term evolution system, in particular to a method and device for realizing interleaving or deinterleaving. Background technique [0002] Interleaving technology is widely used in the communication field to convert burst errors into random errors, so as to reduce the concentration and technical cost of error correction. In order to resist burst errors during transmission, the Physical Downlink Shared Channel (PDSCH) sub-block in the 3rd Generation Partnership Project Long Term Evolution (3GPP LTE) system is performing channel cycling Internal interleaving is performed after convolutional encoding. Similarly, the receiver needs to perform deinterleaving. The 3GPP LTE technical document TS 36.212 describes the sub-block interleaving method. [0003] According to the relevant description in TS 36.212, it can be known that the 3GPP LTE system needs t...

Claims

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Application Information

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IPC IPC(8): H04L1/00
CPCH03M13/2725H03M13/6525H03M13/6505H03M13/276H03M13/2782H04L1/00
Inventor 陈月强张彩虹吕闻曾献君
Owner ZTE CORP
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