Grid stack structure, semiconductor device and manufacturing methods of grid stack structure and semiconductor device

Abstract

The invention provides a grid stack structure and a method for manufacturing the grid stack structure. The grid stack structure comprises an isolation medium layer, wherein the isolation medium layer is formed on a grid and embedded into the grid; a side wall is used for covering the opposite side surfaces of the isolation medium layer; and the isolation medium layer positioned on an active region is thicker than the isolation medium layer positioned on a connecting region. The method for manufacturing the grid stack structure comprises the following steps of: eliminating a part of thickness of the grid, wherein the eliminated thickness of the grid on the active region is greater than the thickness of the grid on the connecting region so as to expose the opposite inner walls in the side wall; and forming the isolation medium layer on the grid, wherein the isolation medium layer covers the exposed inner walls. The invention also provides a semiconductor and a manufacturing method thereof. By the invention, the probability that a short circuit is formed between the grid and a second contact hole can be reduced; and process compatibility can be formed between a first contact hole and the second contact hole.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, in particular, to a gate stack structure, a semiconductor device and a manufacturing method thereof. Background technique [0002] As the critical dimensions of semiconductor devices become smaller and smaller, the size of the contact hole (CA) is also smaller, and the distance between the gate and the contact hole is also reduced. [0003] Among them, one of the topics that major semiconductor companies and research organizations in the world are competing to research and develop is CMOS device gate engineering research. Usually, such as figure 1 As shown, the gate stack structure includes a gate dielectric layer 20 formed on the substrate 10, a gate 40 formed on the gate dielectric layer 20, and spacers surrounding the gate dielectric layer 20 and the gate 40 30. Wherein, the grid 40 is mostly made of a metal grid. Among them, such as figure 2 As shown, the gate 40 is locat...

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Problems solved by technology

[0005] However, in the above process, combined with figure 1 and figure 2 As shown, since the distance between the second contact hole 62 and the gate 40 located in the active region 12 is very close, in practice, due to the limitation of the process, it is easy to connect the second contact hole 62 and the gate 40. A short circuit occurs between 40 (such as image 3 marked by the dotted line 64)

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