Multiprocessor system and multiprocessor exclusive control adjustment method
A multi-processor system and processor technology, applied in the direction of program control design, electrical digital data processing, instruments, etc., can solve problems such as difficult to ensure real-time performance, and achieve the effect of ensuring real-time performance
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Embodiment approach 1
[0043] figure 1 It is a circuit diagram showing the configuration of the multiprocessor system according to Embodiment 1 of the present invention.
[0044] like figure 1 As shown, the multiprocessor system 101 of the first embodiment includes first to fourth processors 1 to 4 . The first to fourth processors 1 to 4 are connected to a common resource 5 through a bus 6 . The first processor 1 includes an exclusive control acquisition priority information storage unit 1a and an exclusive control wait information storage unit 1b. The second processor 2 includes an exclusive control acquisition priority information storage unit 2a and an exclusive control wait information storage unit 2b. The third processor 3 includes an exclusive control acquisition priority information storage unit 3a and an exclusive control wait information storage unit 3b. The fourth processor 4 includes an exclusive control acquisition priority information storage unit 4a and an exclusive control wait in...
Embodiment approach 2
[0070] Figure 4 It is a circuit diagram showing the configuration of a multiprocessor system according to Embodiment 2 of the present invention.
[0071] The basic configuration of the multiprocessor system 201 of the present embodiment is the same as that of the multiprocessor system 101 of the first embodiment, but it is similar to the multiprocessor system 101 of the first embodiment in that it changes the priority of the exclusive control. different. The following description will focus on this point of difference.
[0072] like Figure 4 As shown, in the multiprocessor system 201 of this embodiment, the first to fourth processors 1 to 4 further include exclusive control acquisition attempt count storage units 1c, 2c, 3c, and 4c, respectively. The exclusive control acquisition attempt number storage units 1c, 2c, 3c, and 4c are parts for storing the exclusive control acquisition attempt number, and are composed of circuit elements having a function of storing data. In...
Deformed example 1
[0085] In Modification 1, each of the processors 1 to 4 is configured to change the exclusive control acquisition priority information not based on the number of exclusive control acquisition attempts but in accordance with the priority of the task to be executed or the interrupt process.
[0086] Specifically, each of the processors 1 to 4 updates the exclusive control acquisition priority information during task dispatch processing and interrupt entry / exit processing. For example, when the first processor 1 dispatches a certain task A to another task B, the exclusive control acquisition priority information is changed from the priority of task A to the priority of task B. Also, when an interrupt request of interrupt processing C is generated during execution of task B, and when transitioning to interrupt processing C, the exclusive control acquisition priority information is changed to the priority of interrupt processing C. According to such a configuration, the exclusive c...
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