Single-side gate fin field effect transistor and manufacturing method thereof

Abstract

A single-gate FinFET structure includes an active fin structure having two enlarged head portions and a tapered neck portion that connects the enlarged head portions with an underlying ultra-thin body. Two source / drain regions are doped in the two enlarged head portions respectively. An insulation region is interposed between the two source / drain regions. A trench isolation structure is disposed at one side of the tuning fork-shaped fin structure. A single-sided sidewall gate electrode is disposed on a vertical sidewall of the active fin structure opposite to the trench isolation structure.

Description

technical field [0001] The invention relates to a single-side gate fin-shaped field effect transistor, in particular to a single-side gate fin-shaped field-effect transistor with an ultra-thin base. Background technique [0002] DRAM is a type of random access memory that stores each bit of data in a capacitor on an integrated circuit. Generally speaking, the DRAM is arranged in a square array, and each memory cell is composed of a transistor and a capacitor. As a switching device, the transistor includes a gate and its next silicon channel channel region. The silicon channel region is located in the semiconductor substrate between a pair of source / drain regions, and the gate connects the source / drain regions electrically by controlling the silicon channel region. [0003] At present, the vertical double gate fin field effect transistor has been developed for the next 4F 2 DRAM technology generation, where F represents the minimum line width of the photolithography proces...

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to solve the problem of electrical coupling in DRAM due to the continuous reduction of word line spacing and the like.

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