Distributed test node link and multilink system thereof
A test node and distributed technology, applied in the field of testing and VLSI design, can solve the problems of complex pin testing operations in the background technology, and achieve the effects of saving top-layer metal wiring channels, reducing difficulty, and reducing pin-to-pin work.
Active Publication Date: 2013-12-04
XI AN UNIIC SEMICON CO LTD
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[0008] The present invention provides a distributed test node chain system and its multi-chain system to solve the problem of complex pin test operations in the background technology
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[0024] Such as figure 2 As shown, the entire test system is composed of a test shift controller (TP_SHIFT_MASTER) and a test signal driver (TP_DRIVER). All test signal drivers are connected by three signal lines, which are serial shift signal lines (tp_ser_di), serial Mask signal line (sft_mask) and serial clock signal line (sft_clk). In the present invention, a group of scattered nodes to be tested is connected in series into a chain, and after multi-level driving, the signal to be observed is finally output to a common single port—the final test metal point (HUGE TP). One or more such test node chains can exist on one chip.
[0025] Test shift controller (TP_SHIFT_MASTER):
[0026] Different test shift controllers will be different according to the testable design of the chip. In general, there are two ways to complete the testable design of the chip: one is to provide test pins to complete the testable design, and the other is to provide test commands to complete the te...
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The invention provides a distributed test node link system and a multilink system thereof, and aims to solve the problem that in the background technology, a pin test operation is complicated. A distributed test node link is composed of a test shifting controller and test signal drivers, wherein all the test signal drivers are connected by three signal lines, and the three signal lines respectively are a serial shift signal line (tp-ser-di), a serial mask signal line (sft-mask) and a serial clock signal line (sft-clk). In the invention, through connecting a set of scattered to-be-tested nodes in series so as to form a link, and then carrying out multi-stage driving on the link, signals required to be observed are outputted to a common single port finally. By using the distributed test node link system and multilink system thereof provided by the invention, the difficulty of probe alignment in the process of chip test debugging is reduced, the contact reliability is increased, and the quality of a test signal is improved; and a plurality of signals can be converted conveniently by the shifting controller so as to observe the signals of the to-be-tested nodes, thereby reducing the operation of frequent probe alignment, improving the debugging efficiency, and then shortening the product debugging and development cycles.
Description
technical field [0001] The invention belongs to the technical field of VLSI design and testing, and relates to a serial pin testing circuit, in particular to a distributed testing node chain and its multi-chain system. Background technique [0002] In the design process of integrated circuit chips, engineers usually leave test metal points (Test-pad) near key nodes as needed, and these test metal points can be exposed on the wafer surface during the chip manufacturing process. During the chip testing process, test engineers can use test probes to directly detect these test metal points to observe the signal status of key nodes inside the chip, so as to observe and debug the static and dynamic behavior of the chip, improve debugging efficiency and accuracy, and shorten The debugging cycle and the overall development cycle of the product. [0003] Typically, a schematic for implementing such a testable design would look like figure 1 shown. [0004] S1, S2, S3...Sn is the n...
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IPC IPC(8): G01R31/28G01R1/067
Inventor 江喜平王正文
Owner XI AN UNIIC SEMICON CO LTD