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Bus type test node chain system

A technology for testing nodes and nodes to be tested, applied in the direction of measuring electricity, measuring devices, and measuring electrical variables, etc., can solve complex problems, reduce difficulty, improve test signal quality, and save the effect of top-layer metal wiring channels

Active Publication Date: 2013-09-18
XI AN UNIIC SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The present invention provides a bus-type test node chain system to solve the existing complex problems in design and testing when implementing this testability introduced in the background technology

Method used

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  • Bus type test node chain system
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  • Bus type test node chain system

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Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0024] The entire test system consists of a test shift controller (TP_SHIFT_MASTER), a test signal driver (TP_DRIVER), a final test metal point (HUGE_TP), and a test signal bus (Huge test-pad signal).

[0025] The schematic diagram of the test signal driver is as follows image 3 Shown.

[0026] The test signal driver consists of a register (DFF), a tri-state buffer (TRI_BUF), and a general buffer (BUF) gate.

[0027] Its basic working principle is:

[0028] When the register configuration is completed, if the latched value of the register is 0, the tri-state buffer output high configuration to the test signal line (tp_do=1'bz). If the value of the register latch is 1, the tri-state buffer outputs the signal from the test node to the test metal point signal line (tp_do=tp_di).

[0029] In the register configuration process, the test signal driver outputs the contents of this register to the next level of test signal driver. Generally, the buffer is used to drive the serial clock.

[00...

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Abstract

The invention provides a bus type test node chain system. The bus type test node chain system comprises: n TP-drivers, which are respectively connected to n nodes to be measured; a TP-shift-master, which is used to gate the TP-drivers. The TP-drivers comprise a DFF and a tri-BUF. The tri-BUF possesses a signal input terminal, a data gating terminal and a signal output terminal. The signal input terminal is connected to the nodes to be measured which correspond to a metal point driver. The data gating terminal is connected with a serial shift data output terminal of the corresponding DFF. The signal output terminals of the n tri-BUF are connected to a same huge test-pad signal. An end of the huge test-pad signal is provided with a huge-TP. In the invention, a plurality of scattered test nodes are connected serially into a chain and one large-scale test metal point is shared so that a quantity of the test metal points on a sheet can be reduced and top metal wiring channels can be saved.

Description

Technical field [0001] The invention belongs to the technical field of ultra-large-scale integrated circuit design and testing, and relates to a serial circuit for testing, in particular to a bus-type test node chain system. Background technique [0002] In the design process of integrated circuit chips, engineers usually leave test metal points (Test-pads) near key nodes as needed. These test metal points can be exposed on the surface of the wafer during the chip manufacturing process. During the chip test process, test engineers can use test probes to directly detect these test metal points to observe the signal state of key nodes inside the chip, so as to observe and debug the static and dynamic behavior of the chip, improve debugging efficiency and accuracy, and shorten The debugging cycle and the overall product development cycle. [0003] Under normal circumstances, the schematic diagram to achieve this testable design is as follows figure 1 Shown. [0004] S1, S2, S3...Sn ar...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/3185
Inventor 江喜平冯晓茹
Owner XI AN UNIIC SEMICON CO LTD