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Method, system and dispatcher for simulating multiple processors in parallel

A scheduler and processor technology, which is applied in the field of simulation, can solve problems such as the inability to realize multiple processor debugging, the reduction of simulation efficiency, and the inability to realize parallel simulation of multiple processors, so as to improve resource utilization efficiency, realize debugging, and improve Simulate the effect of efficiency

Active Publication Date: 2014-02-19
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] However, since one processor is scheduled each time, it is impossible to simulate multiple processors in parallel, resulting in a reduction in simulation efficiency. At the same time, debugging when parallel simulation of multiple processors cannot be realized in the prior art

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  • Method, system and dispatcher for simulating multiple processors in parallel
  • Method, system and dispatcher for simulating multiple processors in parallel
  • Method, system and dispatcher for simulating multiple processors in parallel

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Embodiment Construction

[0026] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0027] figure 1 A schematic flowchart of a method for simulating multiple processors in parallel provided by an embodiment of the present invention, such as figure 1 As shown, the method for simulating multiple processors in parallel in this embodiment may include:

[0028] 101. The scheduler maps the debug interface information of the processor...

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Abstract

The present invention provides a method and a system for simulating multiple processors in parallel, and a scheduler. In this embodiment, the scheduler maps debug interface information of a to-be-simulated processor requiring debugging onto the scheduler during parallel simulation of multiple processors, so that the scheduler is capable of debugging, by using a master thread, the to-be-simulated processor requiring debugging via a debug interface of the to-be-simulated processor requiring debugging pointed by the debug interface information, thereby implementing debugging during parallel simulation of multiple processors.

Description

technical field [0001] Embodiments of the present invention relate to simulation technology, and in particular to a method and system for simulating multiple processors in parallel, and a scheduler. Background technique [0002] SIMICS simulator is a high-performance system simulator that can simulate single-processor systems and multi-processor systems. When the SIMICS simulator simulates a multi-processor system, it uses a single processor scheduling method for scheduling, that is, one processor is scheduled to execute the corresponding instruction at a time, so as to realize serial simulation of multiple processors. [0003] However, since one processor is scheduled each time, multiple processors cannot be simulated in parallel, resulting in a decrease in simulation efficiency, and debugging when multiple processors are simulated in parallel cannot be realized in the prior art. Contents of the invention [0004] Embodiments of the present invention provide a method, sy...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/26
CPCG06F11/261G06F30/33
Inventor 叶寒栋曹炯叶笑春王达
Owner HUAWEI TECH CO LTD