Layout method for heterogeneous field programmable gate array (FPGA)

Abstract

The invention discloses a layout method for a heterogeneous field programmable gate array (FPGA). The method comprises the following steps of: laminating different unit types; applying force onto a priority level in a laminated way according to the different unit types; and solving all movable units uniformly. Compared with the conventional FPGA layout algorithm, the layout method has the advantages that: the operation time of the FPGA is reduced; simultaneously, the design performance of the FPGA is improved.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a layout method of a field programmable gate array. Background technique [0002] Field Programmable Gate Array (Field Programmable Gate Array, FPGA) is a product of further development on the basis of programmable devices. It appeared as a semi-custom circuit in the field of application-specific integrated circuits, which not only solved the shortcomings of full-custom circuits, but also overcome the shortcomings of the limited number of original programmable device gate circuits. [0003] In the layout design of FPGA, the rationality of the layout has a great influence on the actual performance of the final FPGA chip. The traditional FPGA layout algorithm runs slowly when dealing with netlists of mixed cells (heterogeneous forms), and the final performance is low. For circuits with high delay requirements, it is difficult to meet the design requirements. For traditional het...

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Problems solved by technology

[0004] The present invention provides a layout method of a heterogeneous field programmable gate array, the purpose of which is to solve the problems of the above traditional heterogeneous FPGA layout method

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