Method and device for remaining signal sequence

Abstract

The embodiments of the invention provide a method and device for remaining signal sequence. When a first FIFO memory is writted with request signal data from a corresponding first upstream device, invalid data are written into a second FIFO memory corresponding to the a second upstream device, in the same time period. The request signal data are read from the first FIFO memory and the invalid data are written from the second FIFO memory. The invalid data are discarded and the request signal data are sent to a downstream device. Through the method and device for remaining signal sequence, coupling degree between devices can be minimized while the remaining signal sequence is realized.

Description

technical field [0001] The embodiments of the present invention relate to communication technologies, and in particular to a method and device for maintaining signal order. Background technique [0002] In communication and network chips, for the communication process of multiple groups of signals between multiple modules with different clock domains, in order to ensure the correctness of data reading and writing, it is necessary to ensure that the sequence of reading and writing requests is consistent with the time sequence, so it is necessary Carry out order processing. [0003] For example, in a complex application scenario: in the first clock cycle, device A requests to read address 0; in the second clock cycle, device B requests to write to address 0; in the third clock cycle, device C requests to read address 0 In the fourth clock cycle, device D requests to read address 0; in the fifth clock cycle, device E requests to write to address 0; in the sixth clock cycle, de...

AI Technical Summary

Problems solved by technology

With this method of signal order preservation, the delay caused by write confirmation will deepen the cache of subsequent request sources, thereby increasing the degree of coupling between modules or devices that require order preservation, and the delay caused by write confirmation will make subsequent requests Intermittent, resulting in unstable system performance, difficult to meet high-quality requirements

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