Settable and resettable D trigger resisting single event upset

An anti-single-event, trigger technology, applied in the direction of electrical pulse generator circuit, reliability improvement modification, pulse generation, etc., can solve the problem of low anti-single-event flipping ability.
CN102394595AActive Publication Date: 2012-03-28NAT UNIV OF DEFENSE TECH
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Patent Information

Authority / Receiving Office
CN Β· China
Current Assignee / Owner
NAT UNIV OF DEFENSE TECH
Publication Date
2012-03-28

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Abstract

The invention discloses a settable and resettable D trigger resisting single event upset, and aims to improve the single event upset resistance of the settable and resettable D trigger. The D trigger comprises a clock circuit, a reset buffer circuit, a main latch, a slave latch and an output buffer circuit, wherein the main latch comprises 14 PMOS (P-channel Metal Oxide Semiconductor) tubes and 14 NMOS (N-Mental-Oxide-Semiconductor) tubes; the slave latch comprises 10 PMOS tubes and 10 NMOS tubes; both the main latch and the slave latch adopt bimodule redundant reinforcement; and in the main latch and the slave latch, C2MOS circuits are also improved, that is, pull-up PMOS tubes and pull-down NMOS tubes in redundant relation in each C2MOS circuit are separated.. The D trigger has strong single event upset resistance, is suitable for standard cell library for a reinforced integrated circuit resisting single event upset, and is used in the fields of aviation, aerospace, and the like.
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Description

technical field

[0001] The invention relates to a master-slave D flip-flop with a settable and resettable structure, in particular to a settable and resetable D flip-flop against single event upset (signal event upset). Background technique

[0002] In cosmic space, there are a large number of high-energy particles (protons, electrons, heavy ions) and charged particles. After the integrated circuit is bombarded by these high-energy particles and charged particles, an electronic pulse will be generated in the integrated circuit, which may cause the original level of the internal node of the integrated circuit to flip. This effect is called single event upset (SEU). The higher the LET (Linear Energy Transfer) value of a single event bombarding an IC, the stronger the resulting electron pulse. Integrated circuits used in aviation and aerospace fields are threatened by single event upsets, which can make integrated circuits work unstable and even cause fatal errors. Therefore, ...

Claims

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