Settable and resettable D trigger resisting single event upset

An anti-single-event, trigger technology, applied in the direction of electrical pulse generator circuit, reliability improvement modification, pulse generation, etc., can solve the problem of low anti-single-event flipping ability.

Active Publication Date: 2012-03-28
NAT UNIV OF DEFENSE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] The technical problem to be solved by the present invention is to propose a settable and resetable D flip-flop against single event reversal for the current problem that the anti-singl

Method used

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  • Settable and resettable D trigger resisting single event upset
  • Settable and resettable D trigger resisting single event upset
  • Settable and resettable D trigger resisting single event upset

Examples

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Example Embodiment

[0030] figure 1 It is a schematic diagram of the logical structure of the D flip-flop capable of being set and reset for anti-single event flip of the present invention. The invention consists of a clock circuit (such as figure 2 Shown), reset buffer circuit (such as image 3 Shown), the main latch (as shown in Figure 4 Shown), slave latch (e.g. Figure 5 Shown) and output buffer circuit (such as Image 6 Shown) composition. The invention has four input terminals and two output terminals. The four input terminals are CK (clock signal input), D (data signal input), SN (set signal input) and RN reset signal input; the two output terminals are Q and QN, Q and QN output a pair Opposite data signal. The clock circuit receives CK, buffers CK and outputs C and CN respectively. The reset buffer circuit buffers RN, inputs R that is inverse to RN, and transfers R to the master latch and the slave latch. The main latch receives D, C and CN, and the main latch latches D under the con...

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Abstract

The invention discloses a settable and resettable D trigger resisting single event upset, and aims to improve the single event upset resistance of the settable and resettable D trigger. The D trigger comprises a clock circuit, a reset buffer circuit, a main latch, a slave latch and an output buffer circuit, wherein the main latch comprises 14 PMOS (P-channel Metal Oxide Semiconductor) tubes and 14 NMOS (N-Mental-Oxide-Semiconductor) tubes; the slave latch comprises 10 PMOS tubes and 10 NMOS tubes; both the main latch and the slave latch adopt bimodule redundant reinforcement; and in the main latch and the slave latch, C2MOS circuits are also improved, that is, pull-up PMOS tubes and pull-down NMOS tubes in redundant relation in each C2MOS circuit are separated.. The D trigger has strong single event upset resistance, is suitable for standard cell library for a reinforced integrated circuit resisting single event upset, and is used in the fields of aviation, aerospace, and the like.

Description

technical field [0001] The invention relates to a master-slave D flip-flop with a settable and resettable structure, in particular to a settable and resetable D flip-flop against single event upset (signal event upset). Background technique [0002] In cosmic space, there are a large number of high-energy particles (protons, electrons, heavy ions) and charged particles. After the integrated circuit is bombarded by these high-energy particles and charged particles, an electronic pulse will be generated in the integrated circuit, which may cause the original level of the internal node of the integrated circuit to flip. This effect is called single event upset (SEU). The higher the LET (Linear Energy Transfer) value of a single event bombarding an IC, the stronger the resulting electron pulse. Integrated circuits used in aviation and aerospace fields are threatened by single event upsets, which can make integrated circuits work unstable and even cause fatal errors. Therefore, ...

Claims

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Application Information

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IPC IPC(8): H03K3/013H03K19/003H03K3/02
Inventor 梁斌李鹏池雅庆刘必慰刘真李振涛陈建军何益百杜延康
Owner NAT UNIV OF DEFENSE TECH
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