System and method for testing universal interface

A test system and general interface technology, applied in error detection/correction, instrumentation, electrical digital data processing, etc., can solve the problems of low serial port data throughput, unable to meet the needs of testing, and the test platform is not fully automated. Achieve the effect of improving test efficiency and reducing test labor costs
CN102479134AInactive Publication Date: 2012-05-30SHANGHAI HUAHONG INTEGRATED CIRCUIT

Patent Information

Authority / Receiving Office
CN Β· China
Current Assignee / Owner
SHANGHAI HUAHONG INTEGRATED CIRCUIT
Publication Date
2012-05-30
Estimated Expiration
Not applicable Β· inactive patent

Smart Images

  • Figure 1
    Figure 1
  • Figure 2
    Figure 2
Patent Text Reader

Abstract

The invention provides a method of a system for testing a universal interface. The system consists of a personal computer (PC) end test script, a communication interface mother board, a communication interface sub-board and a test platform, wherein the test platform is a field programmable gate array (FPGA) or application specific integrated circuit (ASIC) platform; a PC end is connected with the communication interface mother board through a universal serial bus (USB) interface; the communication interface mother board is connected with the communication interface sub-board through a hard wire; the communication interface sub-board is connected with the test platform for test communication; and a communication sub-interface can be made independently according to a test requirement. The invention also provides a method for implementing the system for testing the universal interface. By utilizing the system and the method, the requirement for simultaneously testing by multi-interface test application can be met; the USB interface meets the requirement for high data throughput; and by utilizing the automatic test method, the test labor cost is reduced effectively and the test efficiency is improved.
Need to check novelty before this filing date? Find Prior Art

Description

technical field

[0001] The invention relates to an integrated circuit test system and a test method, in particular to a general interface test system and a test method. Background technique

[0002] With the continuous development of integrated circuit technology and the continuous deepening of the application field of integrated circuits (hereinafter referred to as "IC"), the design complexity and performance complexity of IC chips have been substantially improved compared with before, which is of great importance to chip design companies and chip application manufacturers. The system test plan puts forward higher requirements.

[0003] Currently, IC chip design companies generally adopt two kinds of system testing schemes: first, establish a server-based software chip simulation platform. This solution is mainly aimed at testing the coverage rate of hardware codes and limited module functions; secondly, by building a board-level FPGA (Field Programmable Gate Array) or ASI...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More