Dual-mode redundant system based on lock step synchronization and implement method thereof

A technology of dual-mode redundancy and implementation method, the redundancy applied in hardware is used for data error detection, response error generation and other directions, which can solve the problems of low reliability of dual-mode lockstep system and increase the detection rate. and repair rates, avoid system failures, and improve overall reliability

Active Publication Date: 2012-06-27
SHANGHAI JIAO TONG UNIV
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Problems solved by technology

[0005] In order to overcome the deficiencies in the above-mentioned prior art, the main purpose of the present invention is to provide a dual-mode redundant system based on lockstep synchronization and its implementation method, which solves the problem of low reliability in the dual-mode lockstep system

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  • Dual-mode redundant system based on lock step synchronization and implement method thereof
  • Dual-mode redundant system based on lock step synchronization and implement method thereof
  • Dual-mode redundant system based on lock step synchronization and implement method thereof

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Embodiment Construction

[0026] The implementation of the present invention is described below through specific examples and in conjunction with the accompanying drawings, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific examples, and various modifications and changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0027] figure 1 It is a system architecture diagram of a dual-mode redundant system based on lockstep synchronization in the present invention. Such as figure 1 As shown, a kind of dual-mode redundant system based on lockstep synchronization of the present invention includes a first system 10 and a second system 20, wherein each system includes a computing unit core 11, an interconnection ...

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Abstract

The invention discloses a dual-mode redundant system based on lock step synchronization and an implement method thereof. The system comprises at least a first system and a second system, wherein the first system comprises a computation unit core, an interconnect module, a peripheral bridge, an I/O apparatus, a check control unit, a memory controller, and a memory; and the second system comprises a computation unit core, and also includes at least one of a peripheral bridge, an I/O apparatus, a memory controller and a memory, a check control unit and an interconnect module; the two check control units are connected with the two interconnect modules to simultaneously receive and compare access signals of the two computation unit cores, thereby achieving fault detection. By adding a copy module, the system can improve single-point fault detection rate and repair rate, improve the overall reliability, and obviate system fault caused by single-point failure.

Description

technical field [0001] The invention relates to the field of safety control, in particular to a dual-mode redundant system based on lockstep synchronization and its realization method. Background technique [0002] In some important security industry fields, there are often extremely high requirements for system reliability. The dual-mode lock-step redundant fault-tolerant system replicates the core and operates in lock-step synchronization mode. By comparing the output results, faults in the system operation can be found, which better meets the requirements of system reliability. In the industrial field There are strong application requirements. [0003] In a dual-mode redundant system, the two computing unit cores of the dual-mode backup perform the same action at the same time, and this phenomenon is called lockstep synchronization. However, the current common dual-mode redundant control system with lockstep synchronization is only designed for CPU redundancy, that is, ...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/16
Inventor 张伟蒋江刘婷
Owner SHANGHAI JIAO TONG UNIV
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