Memory array structure with vertical transistor and forming method thereof

Abstract

The invention provides a 4F2 memory array structure with vertical transistors and a forming method thereof. The memory array structure comprises a substrate, a plurality of word lines along the first direction, a plurality of bit lines along the second direction, a plurality of body lines along the first direction and a plurality of memory device contactors. Each of a plurality of memory units located on the substrate comprises a vertical transistor, grid electrodes of the vertical transistors are located in a first groove extending along the first direction and adjacent to semiconductor columns of the vertical transistors. The plurality of word lines are located in the first groove and used for being connected with the grid electrodes. The plurality of bit lines are located on the lower sides of the semiconductor columns and used for being connected with a source region or a drain region located at the lower ends of the semiconductor columns. A first portion of the body lines is located on part of the grid electrodes, and a second portion of the body lines covers the tops of part of the semiconductor columns and used for providing substrate contactors for a vertical channel region. The memory device contactors are located on a source region or a drain region located at the upper ends of the semiconductor columns. By means of the 4F2 memory array structure with the vertical transistors and the forming method, a 4F2 dynamic random access memory (DRAM) array with the substrate contactors can be easily and conveniently achieved.

Description

technical field [0001] The invention relates to the technical field of semiconductor design and manufacture, in particular to a storage array structure with vertical transistors and a forming method thereof. Background technique [0002] In the field of semiconductors, especially memory, methods to increase device integration include reducing device feature size and improving cell structure. However, as the feature size decreases, small-size transistors will produce serious short-channel effects; therefore, by improving the topology of the memory cell, reducing the area occupied by the memory cell under the same feature size is another way to increase the integration of the device. an efficient way. For example, in the field of DRAM (Dynamic Random Access Memory, dynamic random access memory), the existing mainstream process uses 6F2 cells instead of 8F2 cells to significantly increase the integration level of DRAM. figure 1 is the top view of the 6F2 DRAM memory cell arra...

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