Method for manufacturing strain semiconductor device structure

Abstract

The invention provides a method for manufacturing a strain semiconductor device structure. The method comprises the following steps of: providing a front end device structure, which comprises a semiconductor substrate and a grid structure positioned on the semiconductor substrate; forming a partially-ashable interval wall structure which is positioned on both sides of the grid structure and clings to the grid structure on the semiconductor substrate, wherein the partially-ashable interval wall structure comprises a first interval wall layer and a second interval wall layer in sequence from inside to outside; forming protective oxide layers on the surface of the semiconductor substrate, the surface of the partially-ashable interval wall structure and the surface of the grid structure; performing ion injection to form a source / drain region in the semiconductor substrate; removing the protective oxide layers and the second interval wall layer till the surface of the first interval wall layer is exposed; and forming strain introducing liner layers on the surface of the semiconductor substrate, the surface of the first interval wall layer and the surface of the grid structure. According to the method, adverse influences of SPT (Shortest Processing Time) processing on saturated current of a PMOS (P-channel Metal Oxide Semiconductor) transistor can be effectively suppressed, and damages to a siliconization region are avoided.

Description

technical field [0001] The present invention relates to semiconductor manufacturing processes, and in particular, to a method for fabricating strained semiconductor device structures. Background technique [0002] At present, the main factor affecting the performance of field effect transistors is the mobility of carriers, where the mobility of carriers will affect the magnitude of the current in the channel. The reduction in carrier mobility in field-effect transistors not only reduces the switching speed of the transistor, but also reduces the difference in resistance between on and off. Therefore, in the development of complementary metal-oxide-semiconductor field-effect transistors (CMOS), effectively improving carrier mobility has always been one of the key points in transistor structure design. [0003] Conventionally, P-type metal-oxide-semiconductor field-effect transistors (PMOS) and N-type metal-oxide-semiconductor field-effect transistors (NMOS) are treated separ...

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Problems solved by technology

[0008] from figure 1 It can be seen that the saturation current of the PMOS transistor is significantly reduced after being processed by the existing comprehensive SPT technology.

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