Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Semiconductor device

A semiconductor, N-type semiconductor technology, applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve the problem of miniaturization limit and other problems, and achieve the effect of suppressing saturation current

Active Publication Date: 2017-02-22
MITSUBISHI ELECTRIC CORP
View PDF4 Cites 1 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] Since a planar IGBT with a planar MOS structure uses a planar gate, it is necessary to secure an area required for device operation, and there is a limit to miniaturization
In addition, it will be limited by the high turn-on voltage

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Semiconductor device
  • Semiconductor device
  • Semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0039] figure 1 It is a sectional perspective view showing the semiconductor device according to Embodiment 1 of the present invention. figure 2 is in figure 1 The cross-sectional oblique view after omitting the planar gate in the device. image 3 is in figure 1 The cross-sectional oblique view of the device in which the planar gate and gate insulating film are omitted. Figure 4 is along image 3 Sectional view of I-II. In addition, a high withstand voltage class of 6500V was shown in an example as an embodiment, but the present invention can be applied regardless of the withstand voltage class.

[0040] in N － The upper surface of the type semiconductor substrate 1 is provided with a plurality of trenches 2 . A gate trench 4 is provided in the trench 2 via an insulating film 3 . At the mesa portion between trench 2, at N － A planar MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) 5 is provided on the upper surface of a type semiconductor substrate 1 . At...

Embodiment approach 2

[0055] Figure 14 It is a cross-sectional perspective view showing a semiconductor device according to Embodiment 2 of the present invention. Figure 15 is along Figure 14 Sectional view of I-II. The N-type diffusion layer 19 serving as the drain of the planar MOSFET 5 is provided over the entire cell region. N-type diffusion layer 19 and N － type semiconductor substrate 1 connection, with a ratio N － Type semiconductor substrate 1 has a high impurity concentration, and the depth is shallower than that of trench 2 . The N-type diffusion layer 19 serves as a hole blocking layer, and the carrier concentration on the emitter side of the device is increased, so that the on-voltage can be reduced. Other configurations and effects are the same as those of Embodiment 1.

Embodiment approach 3

[0057] Figure 16 It is a cross-sectional view showing a semiconductor device according to Embodiment 3 of the present invention. An N-type diffusion layer 19 is partially provided under the planar gate 14 . The other structures are the same as those in Embodiment 2. Also in this case, the same effects as in Embodiment 2 can be obtained.

[0058] Figure 17 It is a graph showing the conduction voltage of the semiconductor device according to Comparative Example 1 and Embodiments 1 to 3. The evaluation condition is V GE =15V,J C = Rated current density, T j = 25°C. It can be seen that, compared with the first embodiment, the on-state voltage is further lowered in the second and third embodiments.

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
Lengthaaaaaaaaaa
Login to View More

Abstract

The invention discloses a semiconductor device. In a mesa section between trenches (2), a planar MOSFET (5) is provided on the upper surface of an N-type semiconductor substrate (1). In the mesa section, a P+ type emitter layer (6) is provided between the trench (2) and the planar MOSFET (5). A P type collector layer (8) is provided on the lower surface of the N-type semiconductor substrate (1). The planar MOSFET (5) has an N+ type emitter layer (10), an upper section of the N-type semiconductor substrate (1), a P type base layer (12), and a planar gate (14), which is provided on the N+type emitter layer, the upper section of the N-type semiconductor substrate, and the P type base layer with a gate insulating film (13) therebetween. The planar gate (14) is connected to a gate trench (4). The P+type emitter layer (6) has an impurity concentration higher than that of the P type base layer (12), and has an emitter potential equal to that of the N+type emitter layer (10). The N+type emitter layer (10) is not in contact with the trench (2), and a trench-type MOSFET is not configured.

Description

technical field [0001] The present invention relates to a semiconductor device having an insulated gate bipolar transistor (IGBT: Insulated Gate Bipolar Transistor). Background technique [0002] Since a planar IGBT with a planar MOS structure uses a planar gate, it is necessary to secure an area required for device operation, and there is a limit to miniaturization. In addition, it will be limited by high turn-on voltage. On the contrary, in the trench type IGBT, the gate structure is a trench (vertical) structure, so miniaturization can be achieved (for example, refer to Patent Document 1). In addition, the on-voltage characteristics can be improved by utilizing the electron injection effect at the bottom of the trench. [0003] Patent Document 1: Japanese Patent Laid-Open No. 2000-228519 Contents of the invention [0004] However, the trench-type IGBT has problems of high saturation current density and low short-circuit interruption capability due to high active cell...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L29/739H01L29/78
CPCH01L29/407H01L29/0619H01L29/0696H01L29/1095H01L29/7397
Inventor 陈则
Owner MITSUBISHI ELECTRIC CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com