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Increasing dielectric strength by optimizing dummy metal distribution

A pseudo-metal and metal density technology, applied in the field of increasing dielectric strength by optimizing pseudo-metal distribution, can solve problems such as low insertion efficiency

Active Publication Date: 2014-04-23
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Existing insertion processes may suffer from low insertion efficiency

Method used

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  • Increasing dielectric strength by optimizing dummy metal distribution
  • Increasing dielectric strength by optimizing dummy metal distribution
  • Increasing dielectric strength by optimizing dummy metal distribution

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Embodiment Construction

[0030] The making and using of various embodiments of the invention are described in detail below. It should be understood, however, that the present embodiments provide a number of applicable concepts that can be implemented in a variety of specific contexts. The specific embodiments discussed are for illustration only, and do not limit the scope of the invention. Methods for inserting dummy metals and dummy vias are provided according to embodiments. Intermediate stages of various embodiments are shown. Like reference numerals are used to refer to like elements throughout the several views and illustrative embodiments.

[0031] refer to figure 1 , provides a cross-sectional view of a portion of semiconductor wafer 100 . The semiconductor wafer 100 may include active devices such as transistors (not shown) formed on the surface of the semiconductor substrate 20 . An interconnect structure 22 is formed on the surface of the semiconductor substrate 20, the interconnect str...

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Abstract

A method includes providing a wafer representation including a metal layer and a plurality of bump pads over the metal layer, wherein the metal layer includes directly-under-bump-pad regions. A solid metal pattern is inserted into the metal layer, wherein the solid metal pattern includes first parts in the directly-under-bump-pad regions and second parts outside the directly-under-bump-pad regions. Portions of the second parts of the solid metal pattern are removed, wherein substantially no portions of the first parts of the solid metal pattern are removed. The remaining portions of the solid metal pattern not removed during the step of removing form dummy metal patterns. The dummy metal patterns and the plurality of bump pads are implemented in a semiconductor wafer.

Description

technical field [0001] The present invention relates to increasing dielectric strength by optimizing pseudo-metal distribution. Background technique [0002] Dummy metals and dummy vias are used in integrated circuits, for example, to reduce microloading effects in the fabrication process. In an existing process for inserting dummy metals and dummy vias, first, metal lines and metal vias are arranged, and dummy metals and dummy vias are inserted into chip areas not used by the metal lines and metal vias. Existing insertion processes may suffer from poor insertion efficiency. [0003] Therefore, improved methods are needed to provide an insertion process with high insertion efficiency. Contents of the invention [0004] In order to achieve the above object, according to one aspect of the present invention, a method is provided, including: providing a wafer representation, including: a metal layer and a plurality of bump pads located above the metal layer, wherein the meta...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768
CPCH01L2224/13164H01L2224/05155H01L2224/05184H01L24/13H01L2224/05666H01L2924/01019H01L2924/01029H01L2224/13147H01L2224/0401H01L23/522H01L2924/01013H01L2924/014H01L2224/05139H01L2224/05572H01L2224/05124H01L2924/01047H01L2924/01079H01L24/05H01L2224/13155H01L2224/05089H01L2224/05647H01L2924/01005H01L2924/01033H01L2224/05144H01L2924/01074H01L2224/131H01L2924/00014H01L2924/14H01L2224/05552H01L2924/00
Inventor 陈宪伟刘醇鸿
Owner TAIWAN SEMICON MFG CO LTD