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Three-dimensional interconnection structure for air gaps

A technology of three-dimensional interconnection and air gap, which is applied in the field of three-dimensional integration, can solve problems such as large dielectric constant, reliability problems, and affecting high-frequency performance of three-dimensional interconnection, and achieve the effect of reducing manufacturing difficulty and reducing high-frequency capacitance

Active Publication Date: 2014-09-24
北京芯力技术创新中心有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this manufacturing method, the deposition of the insulating layer, the deposition of the diffusion barrier layer and the deposition of the electroplating seed layer are all performed on one side, which requires high requirements on the related manufacturing equipment and manufacturing process, otherwise it is difficult to achieve high-aspect-ratio deep holes. Internally manufacture uniform and complete insulation layer, diffusion barrier layer and plating seed layer, resulting in gaps or holes in copper three-dimensional interconnection, causing reliability problems
In addition, since the insulating layer is usually made of silicon dioxide material, its dielectric constant is large, resulting in a large capacitance composed of three-dimensional interconnect conductors, insulating layers and chip substrates, which affects the high frequency of three-dimensional interconnection in high-frequency applications. performance

Method used

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  • Three-dimensional interconnection structure for air gaps

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0034] like figure 1 As shown, the circuit or sensor chip 1 manufactured by a standard integrated circuit manufacturing process and / or micromachining process first utilizes chemical vapor deposition to deposit a solid material 6 on the upper and lower surfaces of the chip 1, and the solid material is silicon dioxide, and then Reactive ion deep etching technology is used to etch the release groove 5 and the three-dimensional interconnected through hole 2 penetrating the thickness of the chip on the surface of the chip 1, so that the release groove 5 is connected to the through hole 2, and the release groove 5 is covered with an insulating layer of silicon dioxide 6. . The depth of the relief groove 5 is not strictly limited, and may be 1-5 microns, and the shape of the through hole 2 may be circular or polygonal.

[0035] like figure 2 As shown, the organic polymer material is coated on the surface of the chip 1 in the form of a liquid by spin coating, and it penetrates into...

Embodiment 2

[0040] like Image 6As shown, the circuit or sensor chip 1 manufactured by standard integrated circuit manufacturing process and / or micromachining process firstly uses chemical vapor deposition method to deposit solid material 6 on the upper and lower surfaces of the chip 1, the solid material is silicon dioxide, and then Reactive ion deep etching technology is used to etch the release groove 5 and the annular through hole 2 through the thickness of the chip on the surface of the chip 1, so that the release groove 5 is connected with the through hole 2, and the release groove 5 is covered with an insulating layer of silicon dioxide. The depth of the relief groove 5 is not strictly limited, and can be 1-5 microns.

[0041] like Figure 7 As shown, the organic polymer material is coated on the surface of the chip 1 in the form of a liquid by the spin coating method, and the polymer material is made to penetrate deep into the interior of the through hole 2 to fill the interior o...

Embodiment 3

[0047] Adopt the same process of embodiment 1, finish Figure 1 to Figure 4 manufacturing process.

[0048] like Figure 12 As shown in the figure, a suitable cracking and removal method is used to partially remove the material of the organic polymer layer 7 between the through hole 2 and the columnar conductor 3. For example, for polycarbonate, the local heating to 300 degrees can be used. The polycarbonate is decomposed, and the decomposed gas components are discharged through the release tank 5 . By removing the organic polymer layer 7, an air gap is formed between the through hole 2 and the columnar conductor 3, and the three-dimensional interconnection of the air gap is completed.

[0049] Figure 13 A three-dimensional schematic diagram of the finally completed air gap three-dimensional interconnection provided for Example 1 or Example 2.

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Abstract

The invention discloses a three-dimensional interconnection structure of an air gap, which belongs to the technical field of three-dimensional integration. The three-dimensional interconnection structure is composed of through holes penetrating the entire chip and columnar conductors in the through holes, and an annular gap is formed between the through holes and the columnar conductors; the columnar conductors have support heads on at least one side protruding from the upper and lower surfaces of the chip. ; At least one side of the upper and lower surfaces of the chip is etched with a release groove structure on the edge of the through hole, connecting the through hole and the surface of the chip. The three-dimensional interconnection structure of the air gap of the present invention avoids the use of an insulating layer, a diffusion barrier layer and a plating seed layer through the suspended conductor structure, thereby reducing the difficulty of manufacturing the three-dimensional interconnection, and by replacing the insulating layer with an air layer, reducing the Three-dimensional interconnected high-frequency capacitance.

Description

technical field [0001] The invention belongs to the technical field of three-dimensional integration, and in particular relates to a three-dimensional interconnection structure of an air gap. Background technique [0002] The development of integrated circuits basically follows Moore's law, and the degree of integration is constantly developing at a rate of doubling every 18 months. The continuous reduction of feature size and the continuous improvement of integration not only make the feature size of traditional integrated circuits gradually approach the physical limit, but also make integrated circuits encounter development bottlenecks in terms of design, manufacturing and cost. [0003] The continuous shrinking of CMOS devices has continuously improved the integration level. One billion transistors can be integrated in a square centimeter area, and the total length of metal interconnection lines can reach tens of kilometers. This not only makes the wiring extremely compl...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/528H01L23/532
CPCH01L21/76898H01L23/481H01L21/7682
Inventor 王喆垚黄翠陈倩文谭智敏
Owner 北京芯力技术创新中心有限公司