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Low-power-consumption phase accumulator with flow line structure

A phase accumulator and pipeline technology, applied in the direction of automatic power control, electrical components, etc., can solve the problems of increasing circuit power consumption, increasing the difficulty of clock design, etc., to reduce the circuit area, reduce the number, and simplify the design effect.

Active Publication Date: 2014-06-25
迅芯微电子(苏州)股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

A large number of D flip-flops increase the difficulty of clock design and greatly increase the power consumption of the circuit

Method used

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  • Low-power-consumption phase accumulator with flow line structure
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  • Low-power-consumption phase accumulator with flow line structure

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Embodiment Construction

[0020] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0021] Such as figure 2 as shown, figure 2 It is a schematic diagram of a phase accumulator with a low-power pipeline structure according to an embodiment of the present invention, the phase accumulator includes a frequency control word unit 200 and an accumulator unit 300, and the output end of the frequency control word delay unit 200 is connected to the accumulator input to unit 300. Among them, the frequency control word delay unit is used to delay the input frequency control word and then send it to the accumulator unit; The accumulated result is output after hours.

[0022] The phase accumulator is an N-bit accumulator composed of M accumulators with a length of L bits. For the N-bit phase accumulator, an M-sta...

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Abstract

The invention discloses a low-power-consumption phase accumulator with a flow line structure, which abandons a method for increasing delayed time through a cascaded D trigger in a traditional structure and adjusts the delayed time by changing a clock signal of the D trigger in a frequency control word unit, so as to reduce the quantity of the D trigger in the frequency control word unit and reduce the power consumption. With regard to a N-bit phase accumulator with an M-grade flow line structure, the traditional structure needs N*(M+1) / 2 D triggers and the method disclosed by the invention only needs N+M+1 D triggers. The low-power-consumption phase accumulator with the flow line structure disclosed by the invention has the characteristics of simple design, low power consumption and fast frequency change.

Description

technical field [0001] The invention relates to the technical field of integrated circuit phase accumulator design, in particular to a phase accumulator with a low-power pipeline structure applied to a direct digital frequency synthesizer. Background technique [0002] Direct digital frequency synthesizers generate sine or cosine signals with sub-Hz frequency resolution, fast frequency hopping, frequency switching phase continuity, and low phase noise. These advantages make direct digital frequency synthesizers widely used in frequency hopping communication systems. In practical applications, in order to improve the frequency resolution of the direct digital frequency synthesizer, a phase accumulator of more than 32 bits is usually required. At the same time, in order to increase the output frequency range, it is required to increase the operating frequency of the phase accumulator. Since the carry chain of the phase accumulator is a critical path, it becomes the speed bot...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03L7/099H03L7/18
Inventor 陈建武吴旦昱周磊刘新宇武锦金智
Owner 迅芯微电子(苏州)股份有限公司