A method for preparing shallow junctions and sidewalls of an amorphous carbon sacrificial gate structure

Abstract

The invention provides a method for preparing a shallow junction and a side wall of an amorphous carbon sacrificial grid electrode structure. The method comprises the following steps of: firstly, injecting ions into a silicon substrate with a grid electrode pre-preparation structure to form the shallow junction, wherein a grid electrode is arranged on a P-type or N-type well region of the silicon substrate, and a grid oxide layer is arranged between the grid electrode pre-preparation structure and the silicon substrate; preparing the molded grid electrode under an O2 atmosphere environment and removing surface dirt on the silicon substrate and a grid oxidized layer formed in the process of preparing the molded grid electrode; and primarily depositing a first side wall layer and a second side wall layer on the surface of the silicon substrate and the surface of the grid electrode; and etching the side wall to form the first side wall and the second side wall.

Description

technical field [0001] The invention relates to a CMOS semiconductor device integration process, in particular to a method for preparing shallow junctions and sidewalls of an amorphous carbon sacrificial gate structure. Background technique [0002] Chinese patent CN101593686A discloses an integrated process for preparing a metal gate, using amorphous carbon as a sacrificial gate material to form the base structure required by the Gate-last process. The specific process includes: forming a gate dielectric layer on the substrate; forming a patterned amorphous carbon layer on the gate dielectric layer; forming sidewalls surrounding the patterned amorphous carbon layer; forming a patterned the interlayer dielectric layer of the amorphous carbon layer and the sidewall; planarize the interlayer dielectric layer and expose the patterned amorphous carbon layer; remove the patterned amorphous carbon layer by using an oxygen ashing process, A trench is formed in the interlayer diele...

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Problems solved by technology

[0003] The process provided by the above patent is very simple, so many of the processes need to be refined, such as: stacked structure before gate formation; pre-treatment of sacrificial gate formation; post-treatment of sacrificial gate; conventional sidewall structure Formation process; substrate preparation during ion implantation process; SPT process treatment; CESL treatment; CMP process pretreatment, etc.

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