Test system for testing semiconductor-encapsulated stacked wafer and semiconductor automatic test machine thereof
A technology of automated testing and testing systems, which is applied in the direction of single semiconductor device testing, measuring devices, components of electrical measuring instruments, etc., can solve problems such as continuity errors, low yield, and complicated processing steps, and achieve cost savings, The effect of improving efficiency
Active Publication Date: 2015-04-15
致茂电子(苏州)有限公司
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[0004] In the stacked chip package, when the top chip and the bottom chip are stacked and integrated, a final test yield test procedure must be carried out. Therefore, in the conventional stacked chip package, individual top chips must be manually placed on the stack. Individual bottom wafers for final testing; however, once the test results show low yield or continuity errors, it will be difficult to identify the problem with the top wafer or the bottom wafer. If it cannot be identified, seeking other solutions will cause processing Complicated steps
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[0028] The foregoing and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of preferred embodiments with reference to the drawings.
[0029] see figure 1 , which is a test system structure diagram of a test system for testing semiconductor packaging stacked wafers and a semiconductor automatic test machine of the present invention, such as figure 1 As shown, the test system includes a group of test arms 42 located above the test seat 411 and used for vertical movement, and a set of test arms that move back and forth between the position above the test seat 411 and the position away from the test seat 411. Mechanism 43, and this test mechanism 43 includes a group of frame 431, elastic member 432 and probe test device 433, and test seat 411 is arranged on a test board 41; figure 2 As shown, the interior of the probe test device 433 has a carrying surface 4331 and a probe interface board 4332,...
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The invention discloses a test system for testing a semiconductor-encapsulated stacked wafer and a semiconductor automatic test machine thereof. The test system which is used for testing a to-be-tested wafer arranged at a set of testing seat comprises a set of testing arm arranged above the testing seat and a set of testing mechanism moving back and forth between the position above the testing seat and the position far away from the above position of the testing seat, wherein a detection wafer is arranged in the testing mechanism and a plurality of test probes are electrically connected and extend towards the testing seat from the detection wafer. Therefore, when the testing mechanism moves to the position which is between the above position of the testing seat and the testing arm, the testing arm presses the testing mechanism downwards to force a plurality of test probes of the testing mechanism to be closely pressed against the to-be-tested wafer and the detection wafer in the testing mechanism and the to-be-tested wafer are electrically connected to form a set of testing loop in order to perform semiconductor-encapsulated stacked wafer test. Before the stacked wafer is encapsulated, the bottom wafer is automatically classified, so that the testing efficiency is improved and the labor cost is saved.
Description
technical field [0001] The present invention relates to a test machine, especially a test machine with a testing mechanism that moves back and forth between positions above a test seat and has a wafer detection inside. Background technique [0002] Since today's smartphones, mobile computing products, and portable electronic products of various consumer products are all pursuing higher semiconductor functionality and performance at the lowest cost with a limited footprint and minimum thickness and weight; therefore, some manufacturers target individual semiconductor chips. Research and development of the integration, and a stacked multi-package assembly has been developed by stacking chips or by stacking die packages. [0003] The stacked multi-package assembly is generally divided into two categories, one is Package-on-Package (PoP) and the other is Package-in-Package (PiP). In terms of the PoP assembly structure, the current industry standard is 1cm 2 There are more than...
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IPC IPC(8): G01R31/26G01R1/02
Inventor 陈建名
Owner 致茂电子(苏州)有限公司