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Surface modified nano-abrasive silicon slice polishing liquid

A surface modification technology for nanometer and silicon wafer polishing, which is applied in the direction of polishing compositions containing abrasives, etc., can solve the problems of silicon wafer surface damage, complicated cleaning steps, and difficult cleaning, etc., to reduce roughness and improve microscopic conditions Effect

Active Publication Date: 2014-04-02
江苏奥首材料科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when polishing silicon wafers with a polishing solution containing solid abrasives, there is damage to the surface of the silicon wafers, and surface defects such as polishing scratches and pits are prone to occur, resulting in large surface roughness after polishing the silicon wafers. At the same time, polishing Finally, the cleaning steps to remove residual polishing fluid from the surface of the silicon wafer are complicated and difficult to clean

Method used

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  • Surface modified nano-abrasive silicon slice polishing liquid
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  • Surface modified nano-abrasive silicon slice polishing liquid

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0021] Example 1: Polystyrene SiO 2 Modified nano-abrasive 5%;

[0022] Sodium laurylalanine 2%;

[0023] Macrogol 400 2%;

[0024] EDTA 1%;

[0025] Tetramethylammonium hydroxide 1%;

[0026] The balance of pure water, the pH value of the solution is 11.5.

[0027] Prepare the polishing liquid according to the above-mentioned specific implementation method and carry out the polishing experiment. After polishing, the material removal rate is R=780nm, and the surface roughness R a = 0.10 nm.

Embodiment 2

[0028] Example 2: Polystyrene SiO 2 Modified nano-abrasive 20%;

[0029] Sodium laurylalanine 1%;

[0030] Macrogol 400 2%;

[0031] EDTA 1%;

[0032] Tetramethylammonium hydroxide 1%;

[0033] The balance of pure water, the pH value of the solution is 11.2.

[0034] Prepare polishing liquid according to above-mentioned specific implementation method and carry out polishing experiment, the material removal rate after polishing is R=820nm, surface roughness R a = 0.10 nm.

Embodiment 3

[0035] Example 3: Polystyrene SiO 2 Modified nano-abrasive 20%;

[0036] Sodium Octadecylalanine 3%;

[0037] Macrogol 400 2%;

[0038] EDTA disodium salt 1%;

[0039] Tetraethylammonium hydroxide 1%;

[0040] The balance of pure water, the pH value of the solution is 11.4.

[0041] Prepare polishing liquid according to above-mentioned specific implementation method and carry out polishing experiment, the material removal rate after polishing is R=820nm, surface roughness R a = 0.10 nm.

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Abstract

The invention discloses a surface modified nano-abrasive silicon slice polishing liquid capable of reducing the roughness of a polished surface and convenient for cleaning. The surface modified nano-abrasive silicon slice polishing liquid is composed of a surface modified nano-abrasive, an ampholytic surfactant, a high molecular surfactant, a nitrogenous carboxylic acid chelator, organic amine and pure water, wherein the pH value is 10.0-12.0; the mass percent of each raw material is as follows: 5-50% of surface modified nano-abrasive, 1-5% of ampholytic surfactant, 1-5% of high molecular surfactant, 0.5-5% of nitrogenous carboxylic acid chelator, 1-10% of organic amine and the balance being pure water; the surface modified nano-abrasive is composite polymer particles formed by modifying the surfaces of organic polymer particles by using SiO2 or Al2O3; and the diameter of the particles is 200-2000 nm.

Description

technical field [0001] The invention relates to a polishing liquid for chemical mechanical polishing of silicon wafers, in particular to a surface-modified nano-abrasive silicon wafer polishing liquid which can reduce the polishing surface roughness and is easy to clean. Background technique [0002] Silicon wafer is the main substrate material of integrated circuit (IC), and its surface roughness is one of the important factors affecting the etching line width of integrated circuit. With the continuous improvement of integrated circuit integration and the continuous reduction of feature size, the requirements for processing accuracy and surface quality of silicon wafers are also getting higher and higher. At present, the requirements of the Semiconductor Industry Association (SIA) for silicon wafers with a feature size of 0.065-0.13 μm are: the global flatness (GBIR) is less than 2 μm, the surface roughness reaches nanometer and sub-nanometer levels, and the surface has ver...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): C08J5/14C09G1/02
Inventor 侯军崔京南高远
Owner 江苏奥首材料科技有限公司
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