FPGA (Field Programmable Gate Array) realization method for multi-code-length LDPC (Low Density Parity Check) code decoder on basis of hierarchical NMS (Network Management System) algorithm

Abstract

The invention discloses an FPGA (Field Programmable Gate Array) realization method for a multi-code-length LDPC (Low Density Parity Check) code decoder on the basis of a hierarchical NMS (Network Management System) algorithm, which comprises the following steps of: 1) replacing a check matrix of which the code rate is 1 / 2 in a WiMax protocol to obtain a new check matrix, and keeping the performance of the original matrix; 2) applying the new check matrix into a parallel hierarchical iterative decoding structure, generating the read-write address of a storage unit in a decoder by an address generation module, and realizing the design of a multi-code-length decoder; and 3) designing a memory structure according to the characteristics of a QC (Quality Control)-LDPC code in the design, and simultaneously reading and writing in information in each path of parallel processing unit. With the FPGA realization method, the storage volume of updated information in the decoding process is reduced, the information updating speed is effectively improved, the decoder iteration times is reduced, the decoding time delay is greatly lowered by the design structure of the memory, and the decoding efficiency is improved. Meanwhile, wiring is simple by a fixed cable of a storage unit and an updating unit, and the hardware realization difficulty is lowered.

Description

technical field [0001] The invention relates to a multi-mode LDPC code decoder, in particular to a layered iterative decoder with a code rate of 1 / 2 and multiple code lengths in the WiMax protocol. Background technique [0002] Low-density parity-check code (LDPC) is a linear block code based on a sparse check matrix, which has good decoding performance close to the Shannon limit, good distance characteristics, low decoding complexity and low error floor. )Etc. It is one of the most watched research hotspots in the field of channel coding today. It has been widely used in many communication standards, and it is also the preferred scheme of error correction coding in the next generation of broadband mobile communication systems. [0003] WiMax is the abbreviation of Worldwide Interoperability for Microwave Access, that is, global microwave interconnection access. It has been approved by the International Telecommunication Union (ITU) as the fourth global 3G standard after WC...

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Problems solved by technology

[0007] The object of the present invention is to provide a kind of FPGA implementation method of the multi-code length LDPC code decoder based on layered NMS algorithm, solve the storage capacity of updating information in the decoding process of existing multi-code length LDPC codes, and the decoding speed is large. Slow and complex connection between the node update unit and the memory, while realizing normal decoding of IEEE802.16e code rate 1 / 2 and multi-code length LDPC codes, reduce the storage capacity of update information, the number of iterations and node update The complexity of the connection between the unit and the memory makes the decoding speed faster and easier for hardware design and implementation

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