rc extraction for single patterned spacer technology

Abstract

The present invention provides a method comprising performing a place and route operation using an electronic design automation tool to form an initial layout of a photomask to be used to form a circuit pattern of a semiconductor device. Place and route operations are regulated by a number of Single Pattern Spacer Technology (SPST) routing rules. The dummy conductive fill pattern is simulated in an EDA tool using an RC extraction tool to predict the location and size of the dummy conductive fill pattern that will be added to the original layout of the photomask. RC timing analysis of the circuit pattern is performed in the EDA tool based on the initial layout and the simulated virtual conductive fill pattern.

Description

technical field [0001] The present subject matter relates generally to semiconductor fabrication and, more particularly, to the fabrication of small circuit geometries using electronic design automation tools. Background technique [0002] In semiconductor fabrication processes, the resolution of photoresist patterns begins to blur at a half-pitch of about 45 nanometers (nm). In order to continue to utilize manufacturing equipment purchased for larger technology nodes, double exposure methods have been developed. [0003] Double exposure involves patterning a single layer of a substrate using two different masks in succession on the same layer of the substrate. A set of first patterns is formed using the first mask. The patterns in the second mask are positioned so as to form second patterns interposed between the first patterns formed by the first mask. As a result, the minimum line spacing in the combined pattern can be reduced while maintaining better resolution. In a...

AI Technical Summary

Problems solved by technology

Although DPT has many advantages, its operation is relatively intensive

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