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Broadcast channel (BCH) parallel coding circuit

A coding circuit and circuit technology, applied in cyclic codes, using linear codes for error correction/detection, using block codes for error correction/detection, etc., can solve the problems of low large-scale data processing capacity and inability to meet FlashMemory transmission efficiency, etc. , to achieve the effect of meeting the requirements of transmission efficiency and improving coding efficiency

Inactive Publication Date: 2015-04-01
UNIV OF JINAN
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  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The BCH serial encoding circuit can only process one bit of data at a time, and the processing capacity of large-scale data is very low, so it cannot meet the requirements of Flash Memory transmission efficiency

Method used

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  • Broadcast channel (BCH) parallel coding circuit
  • Broadcast channel (BCH) parallel coding circuit
  • Broadcast channel (BCH) parallel coding circuit

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Embodiment Construction

[0017] A further detailed description will be made below in conjunction with the accompanying drawings and preferred embodiments.

[0018] see figure 1 , first introduce the BCH serial encoding algorithm:

[0019] The BCH serial encoding circuit is a kind of system cyclic code, so it can be realized by the system encoding circuit in principle, and a system encoding circuit will decode through the following three steps in principle:

[0020] (1) Shift the information code word m(x) to the left n-k bit, ready to use multiplied by the message polynomial m ( x ),which is , where m(x) is a polynomial about x, shift the coefficients about x in m(x) to the left n - k bit, equivalent to x n-k m(x);

[0021] (2) Using generator polynomials g ( x )remove get remainder b ( x );

[0022] (3) generate code word polynomial ;

[0023] Secondly, the generation formula of the BCH code generator polynomial g(x) is introduced:

[0024] Assume Yes ( Represents the m-t...

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Abstract

The invention discloses a broadcast channel (BCH) parallel coding circuit which is characterized by comprising a 8-bit information input end mi, wherein 0<=i <8; a group of check code registers bj,1<=j<=t, wherein t is the number of the check code registers; and an exclusive or circuit group S1j,1<=j<=t, wherein t is the number of the check code registers, each exclusive or circuit group S1j comprises eight exclusive or circuits, and the 8-bit information input end mi is connected onto exclusive or circuit groups Sj respectively. The BCH parallel coding circuit can simultaneously process eight information bytes in one clock period, eight bytes of data are input into the parallel coding circuit, corresponding check code registers update the data, and check code register values obtained after inputting of all information code words is finished are the generated check codes. The improved BCH parallel coding circuit corrects random errors in a flash memory and is remarkably improved in coding efficiency.

Description

technical field [0001] The present invention designs the technical field of BCH encoding, and in particular relates to a BCH parallel encoding circuit. Background technique [0002] The data storage and management of embedded products is an essential research topic in the development of embedded products. With the fast speed, large capacity and low cost of Flash Memory being recognized by more and more companies, Flash Memory is widely used as a storage device for various embedded products. And for different product applications, Flash Memory, as the mainstream storage device of the current embedded system, is widely used in people's lives in various forms. However, the rapid development of Flash Memory has also made data storage security a bottleneck in the development of various embedded products. Due to the improvement of Flash Memory manufacturing process and chip integration, data errors may occur in the Flash Memory storage arrays used in daily life, such as data err...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/15
Inventor 孙涛周莉程彪
Owner UNIV OF JINAN