Unlock instant, AI-driven research and patent intelligence for your innovation.

Source follower input buffer

A source follower and buffer technology, applied in the buffer field, can solve problems affecting spurious-free dynamic range, etc.

Active Publication Date: 2015-07-08
TEXAS INSTR INC
View PDF14 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Such a configuration with this extra small capacitor C1 constraint can be problematic not only in terms of its inability to drive switching loads, but when used in an interleaved ADC it can also significantly and adversely affect the spurious free dynamic range (SFDR) of the interleaved ADC , the interleaved ADC uses many buffers to drive multiple S / H circuits

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Source follower input buffer
  • Source follower input buffer
  • Source follower input buffer

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0022] figure 2 An interleaved analog-to-digital converter (ADC) 200 according to an example embodiment of the invention is illustrated. In operation, analog input signal AIN is provided to buffers 202-1 through 202-n (where each buffer is coupled to bias circuit 212). The output from each buffer 202-1 through 202-n is coupled to a corresponding sample-and-hold (S / H) circuit 204-1 through 204-n so that the input signal AIN can be sampled and provided to a corresponding ADC pipeline 206- 1 to 206-n for conversion. Clock circuit 210 coupled to S / H circuits 204-1 through 204-n and ADC pipelines 206-1 through 206-n provides timing signals to sample and convert input signal AIN to a digital signal. The interleaved digital output signals from ADC pipelines 206-1 through 206-n are then multiplexed by multiplexer (or mux) 208 to generate digital output signal DOUT.

[0023] image 3 A more detailed view of bias circuit 212, buffers 202-1 and 202-2, and S / H circuits 204-1 and 204-2...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

Traditionally, input source follower buffers for analog-to-digital converters (ADCs) lacked sufficiently high linearity. This was due in part to source follower buffers having to drive external capacitive loads by generally providing a signal current to the capacitive load. Here, a buffer is provided that includes a source follower buffer and other biasing circuitry (which provided the signal current). Thus, the overall linearity of the input circuitry (namely, the input buffer) is improved.

Description

technical field [0001] The present invention relates generally to buffers, and more particularly to source follower buffers with reduced input capacitive loading. Background technique [0002] Referring to Figure 1 of the drawings, reference numeral 100 generally indicates a conventional input circuit for an analog-to-digital converter (ADC). Circuit 100 is generally described in co-pending patent application Ser. No. 12 / 199,804, which is hereby incorporated by reference for all purposes. As shown, circuit 100 generally includes a transmit medium (represented by inductor L1 ), buffer 102 , and sample-and-hold (S / H) circuit 104 . Buffer 102 generally includes NMOS transistor Q1 (which is coupled to inductor L1 ), cascoded NMOS transistors Q2 and Q3 (which receive bias voltages NCAS and NBIAS at their respective gates), and capacitor C1 . The S / H circuit 102 is generally (for ease of illustration) denoted as a resistor RS, a sampling switch SS, and a sampling capacitor CS. ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/0175H03M1/12
CPCH03K19/018528G11C27/024
Inventor 尼婷·阿加瓦尔维斯维斯瓦拉亚·A·彭塔科塔
Owner TEXAS INSTR INC