Internal clock gating apparatus

Abstract

An internal clock gating apparatus comprises a static logic block and a domino logic block. The static logic block is configured to receive a clock signal and a clock enable signal. The domino logic block is configured to receive the clock signal and a control signal from an output of the static logic block. The static logic block and the domino logic block are further configured such that an output of the domino logic block generates a signal similar to the clock signal in phase when the clock enable signal has a logic high state. On the other hand, the output of the domino logic block generates a logic low signal when the clock enable signal has a logic low state. Furthermore, the static logic block and the domino logic block can reduce the setup time and delay time of the internal clock gating apparatus respectively.

Description

technical field [0001] The invention relates to the field of integrated circuits, and more specifically, to an internal clock gating device. Background technique [0002] Various battery powered portable devices such as mobile phones, notebook computers, etc. have become popular. Each portable device may utilize multiple integrated circuits. To extend the battery life of portable devices, the power consumption of integrated circuits becomes a concern. Various energy saving methods have been adopted, thereby improving the power consumption of portable devices. Among these methods, reducing clock network power consumption is an effective method, thereby reducing the overall power consumption of modern portable devices including several high-performance digital systems. [0003] Digital systems may include various synchronization circuits that require a clock to synchronize all components. When the semiconductor technology is further developed, the frequency of the clock si...

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Also, longer latency times may prevent the core processor unit from ac

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