Chip-on-glass (COG) interconnection resistance prediction method based on machine vision

Abstract

The invention discloses a COG interconnection resistance prediction method based on machine vision. The method comprises capturing the picture of a bump of a driving chip of a display module; subjecting the picture to computer vision treatment to obtain the number of conductive particles corresponding to the bump as well as the contact area between each conductive particle and the bump; calculating the interconnection resistance of each conductive particle by using an interconnection resistance calculation model based on the contact area of the conductive particles; and obtaining the interconnection resistance between the bump and an electrode by using the interconnection resistances of the plurality of conductive particles as a plurality of parallel resistances. The COG interconnection resistance prediction method provided by the invention can be used for predicting the interconnection resistance between the bump of the drive chip of the display module with COG package and the electrode of a glass substrate online or offline, and has the advantages of high accuracy and strong function.

Description

technical field [0001] The invention relates to a method for predicting interconnection resistance, in particular to a method for predicting interconnection resistance based on machine vision for a display module packaged on glass. Background technique [0002] Flat-panel display series products are the most widely used human-computer interaction medium in the modern information society. It plays a pivotal role in civilian, commercial and military fields, such as flat-panel TVs, mobile phones, and notebook computers. . In the manufacturing process of flat-panel displays, Chip on Glass (COG) is a key production technology, which was first developed by Japanese companies in the 1980s and applied to the production of portable TV displays. It has the advantages of high density, low cost, high efficiency, and small size. With the continuous development of flat panel display in the direction of high density and large capacity, it has become the dominant packaging interconnection ...

AI Technical Summary

Problems solved by technology

Obviously, the former method is expensive and requires a lot of labor, and because of the large number of driver chip pins, this method cannot quickly find the bumps of abnormal interconnection resistance; the latter method only provides an empirical index after statistics, and the evaluation standard is vague There is no corresponding quantitative resistance characteristic, and it is only used as a reference control of the former method in existing packaging companies (usually engineers manually count conductive particles through an optical magnifying glass)

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