Processor, device and method for carrying out cache prediction

Abstract

The invention discloses a processor, a device and a method for carrying out cache (Cache) prediction. The processor comprises a multi-level cache, a memory access component and a main memory, and also comprises a cache prediction executing device, a prediction data block register, a processor prediction executing bit and an instruction prediction executing bit; the cache prediction executing device comprises a cache hit comparison unit, a prediction executing unit and a prediction executing rollback submitting unit; the processor compares whether a state bit of the cache block corresponding to the memory access address is valid (Valid), and determines whether cache prediction is carried out, carries out prediction execution if cache prediction occurs, controls the memory access component to take back the memory access result, determines whether the prediction execution result is directly submitted or rolled backwards according to the memory access result, and executes again from a prediction point. According to the device, mean access time delay of the processor can be effectively reduced, and the performance of the processor is improved.

Description

technical field [0001] The present invention relates to the technical field of implementing a computer processor, in particular to a processor, device and method for cache prediction execution when a cache (Cache) block becomes invalid. Background technique [0002] With the improvement of the internal main frequency of the processor and the optimization of the structure, the computing performance of the processor is getting higher and higher, but the access speed of the main memory does not increase synchronously, so the problem of the memory wall (Memory Wall) appears. . In order to solve this problem, modern processors generally alleviate the problem by adding a multi-level cache (Cache). [0003] In a multi-core processor, each processor core generally has its own private cache (Cache), which will lead to the problem of inconsistency in data backup of private caches (cache) in different processor cores. In order to solve this problem, modern processors support various ...

AI Technical Summary

Problems solved by technology

[0004] However, there is a problem of false sharing in this method. In order to save cache (Cache) space and improve cache (Cache) utilization, the cache block (Cache Line) of modern processor cores is generally 256 bits, or 512 bits, and The actual memory access operation often only accesses 8-bit, 16-bit or 32-bit data

And because invalidation is invalidated in units of cache blocks, even if one bit of data in the entire cache block is modified, the entire cache block will be invalid. Instructions can continue to be executed only when they are retrieved from the first-level cache or main memory, which greatly wastes time and efficiency and reduces the performance of the processor.

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