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Device and method for improving maintenance efficiency of 283-series digital signal processor

An efficient and series technology, applied in the field of improving the maintenance efficiency of 283 series DSP, it can solve the problems of abnormal CPU operation, reduce product reliability, and leave room for operation, so as to improve program maintenance efficiency, reduce hardware cost, and operate simple and fast. Effect

Active Publication Date: 2015-01-07
WISDRI WUHAN AUTOMATION
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When the program is encrypted, in addition to setting the Flash password, you also need to pay attention to the location of the program code in the DSP program memory area, otherwise the CPU cannot run normally; when the encrypted program is upgraded and maintained, only entering the password is invalid, and the startup must be changed. mode, the emulator can be used for debugging, which has caused a lot of inconvenience to the manufacturer
[0004] In order to solve this problem, most manufacturers use DIP switches or buttons. Before powering on, switch the DIP switch or button to the startup mode selection state, and restore it to the FLASH startup state after maintenance. However, DIP switches and The buttons all need to be manually operated, and an operating space needs to be reserved on the structural shell, which increases the difficulty of structural and hardware design, and may reduce product reliability

Method used

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  • Device and method for improving maintenance efficiency of 283-series digital signal processor
  • Device and method for improving maintenance efficiency of 283-series digital signal processor

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Embodiment Construction

[0020] figure 1 It is the working principle figure of an embodiment of the present invention, and present embodiment device comprises the CPLD that is connected with DSP, comprises frequency divider and time delay device in CPLD; Wherein the input end of frequency divider is connected with the clock input end of DSP; Time delay One input terminal of the delayer is connected to the output terminal of the frequency divider, the other output terminal is connected to the reset input terminal of the DSP, and the output terminal of the delayer is connected to the GPIO86 / XA14 and GPIO87 / XA15 pins of the DSP at the same time. The reset signal RST and the system clock signal CLK are sent to the CPLD and DSP at the same time. Inside the CPLD, firstly, the clock signal with a lower frequency is obtained by dividing the frequency of the clock signal CLK, and then the clock signal with a lower frequency is used to reset the reset signal. RST counts and delays, and sends its output to the p...

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Abstract

The invention provides a device and a method for improving the maintenance efficiency of a 283-series digital signal processor. The device comprises a frequency divider and a delayer, which are connected with the DPS. The input end of the frequency divider is connected with the clock input end of the DSP. One input end of the delayer is connected with the output end of the frequency divider, the other input end of the delayer is connected with the resetting input end of the DSP, and the output end of the delayer is connected with pins GPIO86 / XA14 and GPIO87 / XA15 of the DSP. A clock signal is simultaneously transmitted to the frequency divider and the DSP. The frequency divider performs frequency division on the clock signal to obtain a low-frequency clock signal, and transmits the low-frequency clock signal to the delayer. A resetting signal is simultaneously transmitted to the delayer and the DSP. The delayer performs counting delay on the resetting signal by using the clock signal, and outputs the resetting signal to the pins GPIO86 / XA14 and GPIO87 / XA15 of the DSP. An operator finishes connecting a simulator and the DSP within the delay time of the delayer.

Description

technical field [0001] The invention is applied to all products using 283 series DSP as the main control chip, and specifically relates to a method for improving maintenance efficiency of 283 series DSP. Background technique [0002] The 283 series DSP is the 32-bit high-end CPU mainly promoted by TI. It supports floating-point calculations. Compared with the 281 series, the event manager and AD modules have been greatly improved, and are more suitable for the majority of programmers. Wide range of applications. [0003] Compared with the previous DSP or single-chip microcomputer, 283 series DSP is more rigorous in encryption and decryption. When the program is encrypted, in addition to setting the Flash password, you also need to pay attention to the location of the program code in the DSP program memory area, otherwise the CPU cannot run normally; when the encrypted program is upgraded and maintained, only entering the password is invalid, and the startup must be changed....

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/76
Inventor 康现伟王胜勇卢家斌刘亮李传涛李四川李海东
Owner WISDRI WUHAN AUTOMATION
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