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Cache-coherence multi-core processor data transmission system based on no-write allocation

A data transmission system and multi-core processor technology, applied in the direction of electrical digital data processing, instruments, digital computer components, etc., can solve the problems of long access delay and low performance, and achieve the effect of reducing access operations

Active Publication Date: 2015-05-13
C SKY MICROSYST CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In some cases, the processor will frequently initiate access to the shared memory, and the performance is very low due to the high latency of the access to the shared memory
This is why most commercial multicore processors do not use non-write allocated caches

Method used

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  • Cache-coherence multi-core processor data transmission system based on no-write allocation
  • Cache-coherence multi-core processor data transmission system based on no-write allocation
  • Cache-coherence multi-core processor data transmission system based on no-write allocation

Examples

Experimental program
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Effect test

example 1

[0092] Example 1: Reference Figure 5 ~ Figure 8 , taking a multi-core processor system composed of four processors as an example, the processing of various situations in various operations by a cache coherency protocol based on non-write allocation proposed by the present invention is illustrated.

[0093] Regarding read hit operations, such as Figure 5 Shown: Processor 1 read hit, the state of the cache line may be Exclusive Modified State (ED), Exclusive Clean State (EC), Shared Clean State (SC) or Shared Modified State (SD), at this time processor 1 The cache served data, the state of the cache line is unchanged.

[0094] Regarding read miss operations, such as Image 6 Shown: Processor 1 reads a miss, needs to get data, and allocate the cache line. Processor 1 sends a read miss request. After processors 2, 3, and 4 receive the read miss request, they check their respective caches. If there is no valid cache line or the cache line is in the shared clean state (SC), giv...

example 2

[0097] Example 2: Reference Figure 9 , taking a multi-core processor system composed of four processors as an example, the workflow of a hardware device for implementing the non-write allocation-based cache coherency protocol proposed by the present invention is described.

[0098] Such as Figure 9 As shown, when processor 1 generates a read miss, write miss or write hit in a cache line in a shared state (SD or SC), it will perform the following steps.

[0099] In the first step, the processor 1 sends a consistency message to the monitoring management unit through the consistency request interface. Among them, the consistency request interface includes: a consistency request signal, used to indicate whether the consistency request is valid; a consistency type signal, used to indicate whether the consistency operation is a write hit, a write miss, or a read miss; an address signal, used to indicate On which address the processor generates a consistency request; write data s...

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Abstract

The invention relates to a cache-coherence multi-core processor data transmission system based on no-write allocation. The multi-core processor data transmission system comprises a monitoring management unit, at least two processors, an on-chip interconnection bus and a shared storage, wherein at least two processors adopt a wire-back cache and adopt no-write allocation strategy in write-miss process, when one processor has consistency operation, relevant information on the consistency operation can be sent to the monitoring management unit, and the processer can complete the consistency operation after the monitoring management unit processes and gives a response. The invention provides a cache-coherence multi-core processor data transmission system based on no-write allocation, which reduces the access operation to the shared storage, shortens the average access delay and promotes the performance of the processor.

Description

technical field [0001] The invention relates to the field of multi-core processors, in particular to a multi-core processor data transmission system. Background technique [0002] Multicore processor systems based on symmetric shared memory support caching of both shared and private data. Private data is used by a single processor, while shared data is used by multiple processors. The system basically completes the communication between processors by reading and writing shared data. Due to the existence of shared data, multiple versions of the same data may exist in the shared memory and caches of multiple processors at the same time. If more than one processor is writing to the data at this time, inconsistencies may occur, resulting in errors in program execution. The cache coherence protocol is a mechanism for ensuring data consistency in the caches of each processor in a multi-core processor system. The coherence protocol can be implemented by software or hardware. The...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/167
Inventor 严晓浪修思文黄凯葛海通
Owner C SKY MICROSYST CO LTD
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