Shift register, grid line integrated drive circuit, array substrate and display

Abstract

The invention discloses a shift register, a grid line integrated drive circuit, an array substrate and a display. Two electronic switch modules are additionally arranged in the conventional shift register and are arranged between a drop-down node, a low level signal end and a pull-up node, and between the drop-down node, the low level signal and a signal output end respectively; the two electronic switch modules are started when the shift register is in the non-work time and the drop-down node is in low level and are used for reducing the noise of discharging the pull-up node and the signal output end respectively, so that the noise interference of the shift register in the non-working time is effectively reduced.

Description

technical field [0001] The invention relates to the field of display technology, in particular to a shift register, a gate line integrated drive circuit, an array substrate and a display. Background technique [0002] In a thin film transistor liquid crystal display (TFT-LCD, Thin Film Transistor Liquid Crystal Display), usually a gate driving device provides a gate driving signal to the gate of each thin film transistor (TFT, Thin Film Transistor) in the pixel area. The gate drive device can be formed on the array substrate of the liquid crystal display through an array process. This integration process not only saves costs, but also achieves a symmetrical and beautiful design on both sides of the liquid crystal panel (Panel). At the same time, it also eliminates the need for gate integration. Circuit (IC, Integrated Circuit) bonding (Bonding) area and fan-out (Fan-out) wiring space, so that narrow border design can be realized; moreover, this integration process can also s...

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Problems solved by technology

[0004] It can be seen that the signal input terminal (INPUT), the reset signal terminal (RESETIN) and the signal output terminal (OUTPUT) are all low level, when the clock signal terminal (CLKIN) is high level, the parasitic capacitance Cgd1 of T101 is coupled To the PU node, the drain current of T101 increases, so that the potential of the signal output terminal (OUTPUT) rises, and since T103, T104 and T102 are all cut off during non-working hours, when the signal output terminal (OUTPUT) is affected When the potential rises due to the influence of the CLKIN terminal, there is no pull-down transistor to reduce the voltage of the signal output terminal (OUTPUT), so that the output signal of the signal output terminal (OUTPUT) generates relatively large noise

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