Four-stage addressing method for tile recording disk

An addressing method and technology of tile recording, which is applied in the field of four-level addressing of tile recording disks, can solve the problems of poor random write performance of tile recording disks, reduce data coverage, reduce write amplification factor, and reduce interval interval overhead Effect

Inactive Publication Date: 2013-03-27
HUAZHONG UNIV OF SCI & TECH
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Problems solved by technology

[0009] In view of the defects of the prior art, the purpose of the present invention is to provide a four-level addressing method for tile recording disks, which optimizes the data structure and track layout of tile recording disks for the random write restrictions of tile recording disks, and combines flash memory With the ad

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  • Four-stage addressing method for tile recording disk
  • Four-stage addressing method for tile recording disk
  • Four-stage addressing method for tile recording disk

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Embodiment Construction

[0054] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0055] The four-level addressing method of tile recording disk of the present invention comprises the following steps:

[0056] (1) Divide the logical space of the tile recording disk into a four-level structure of "area-segment-block-sector". A segment contains multiple blocks, and a block consists of multiple consecutive sectors, thus forming a four-level division structure of "area-segment-block-sector", such as figure 2 As shown in , each ring represents a zone, and a zone is divided into several segments in the radial direction. For example, area 1 is divided into 8 segments, and each segme...

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Abstract

The invention discloses a four-stage addressing method for a tile recording disk. The four-stage addressing method comprises the following steps of: dividing a logic space of the tile recording disk into a four-stage structure comprising a region, a section, a block and a sector; addressing the divided four-stage structure by a radial addressing mode; optimizing region intervals of the divided four-stage structure by adopting symmetric stack type magnetic track arrangement; and performing read-write operation on the tile recording disk with the addressed four-stage structure. Aiming at tile recording disk random write limitation, a data structure and the track arrangement of the tile recording disk are optimized; due to the advantages of high read-write speed of a flash memory and a memory, a tile recording disk system with a three-stage architecture is formed, so that the problem of low random write performance of the conventional tile recording disk is solved; the available capacity of the disk can be multiplied, and the performance can be prevented from being reduced; and the read-write speed is increased.

Description

technical field [0001] The invention belongs to the technical field of data storage, and more specifically relates to a four-level addressing method of a tile recording disk. Background technique [0002] The vigorous development of the Internet and the digital transformation of society have led to an explosive growth of digital data. According to statistics from the market analysis company IDC and the storage device company EMC, the total amount of global data content was 161EB in 2006, 281EB in 2007, 487EB in 2008, and an astonishing 1800EB in 2011. The total amount of data has grown more than 11 times from 2006 to 2011, growing exponentially at a rate of 61% per year. IDC predicts that the total number of files will increase by 75 times in the next 10 years. Explosive information growth will inevitably lead to a substantial increase in the demand for storage capacity. At the same time, the continuous rapid growth of storage demand poses an important challenge and oppor...

Claims

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Application Information

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IPC IPC(8): G06F12/02
Inventor 万继光谢长生谭志虎陈鹏赵楠楠毛宇王继彬
Owner HUAZHONG UNIV OF SCI & TECH
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