Optimization method of capturing power consumption in scan test

Abstract

The invention discloses an optimization method of capturing power consumption in a scan test. The optimization method of capturing power consumption in the scan test comprises the following steps: generating a netlist with a scan chain; grouping gating control clock units; designing a power constrain unit; combining with the generated netlist with the scan chain, conducting chip layout design which comprises a floorpan, a layout, a clock tree sythesis and wiring; reading a gate-level netlist with a scan structure, a process library, a timing sequence constrain file and a test protocol into an automatic test vector generating tool after the chip layout design is completed, conducting testability design rule checking, and generating a test vector; and conducting gate-level simulation to the test vector generated. By means of the optimization method of capturing the power consumption in the scan test, the capturing power consumption in a test process can be reduced significantly, the reduction of coverage or the sharp increase of the quantity of test vectors is not generated, changing of a test design process is needless, and realization is easy.

Description

technical field [0001] The invention belongs to the technical field of chip low power consumption test design, and in particular relates to an optimization method aiming at capturing power consumption in scanning test. Background technique [0002] With the continuous shrinking of the physical size of integrated circuits and the continuous reduction of voltage thresholds, power consumption, performance, and area have become the most important design indicators for system chip design. In the last decade, low-power design based on algorithms, architectures, and circuits has attracted great attention, and chip designers are increasingly adopting low-power designs to meet increasingly difficult power consumption challenges. While low-power design methodologies can address power consumption issues that arise in the design of complex digital systems, they are not very effective for power consumption in test modes. Studies have shown that the power consumption of LSI in test mode ...

AI Technical Summary

Problems solved by technology

Similar to reducing the test clock frequency, this method also increases the test time

Moreover, this block test method needs to modify the circuit design, such as adding a multiplexer to select between multiple block signals, which leads to an increase in the complexity of the test design.

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