pmos embedded low voltage trigger scr device for esd protection

Abstract

The invention relates to a PMOS embedded low-voltage trigger SCR device for ESD protection. The technical scheme adopted is: an N well is arranged on the P-type substrate, a first N+ implantation region and a first P+ implantation region are arranged on the N well, and the first P+ implantation region is adjacent to the junction of the N well and the P-type substrate, The first N+ injection region and the first P+ injection region are connected to the anode. A third N+ implantation region and a second P+ implantation region are provided on the P-type substrate, the third N+ implantation region is adjacent to the junction of the N well and the P-type substrate, and the third N+ implantation region and the second P+ implantation region are connected to the cathode. The second N+ implantation region is connected between the N well and the P-type substrate; the second N+ implantation region is used as a drain of the NMOS, and the third N+ implantation region is used as a source of the NMOS. The PMOS gate is connected to the anode, the drain is connected to the NMOS gate, the source is connected to the anode, and the substrate is connected to the Vdd of the circuit. The invention adopts a new technology to reduce the ESD trigger voltage of the device.

Description

technical field [0001] The invention relates to an electrostatic protection (ESD) device applicable to a 65nm semiconductor process, in particular to an SCR device triggered by a low voltage. Background technique [0002] Semiconductor processing technology enables the production of extremely small transistors. These tiny transistors have thin oxide insulating layers that are easily damaged by static electricity. Therefore, special care is required when handling these semiconductor devices. [0003] Electrostatic discharge (ESD, Electron Static Discharge) is an instantaneous process in which a large amount of static charge is poured into the integrated circuit from the outside to the inside when the pins of an integrated circuit are floating, and the whole process takes about 100ns. When the electrostatic discharge of the integrated circuit will generate hundreds or even thousands of volts of high voltage, the gate oxide layer of the input stage in the integrated circuit w...

AI Technical Summary

Problems solved by technology

However, the trigger voltage of traditional thyristor ESD protection devices is very high

Images