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A ccd drive sequence processing device

A technology for driving timing and processing devices, which is applied in the field of imaging, can solve problems such as complex implementation schemes, low implementation costs, and difficulty in upgrading and updating CCD drive timing, and achieve the effect of solving the difficulty of upgrading and updating and achieving low cost

Active Publication Date: 2016-04-13
ZHEJIANG UNIVIEW TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] Compared with the prior art, the present invention not only solves the problem of the prior art by storing the CCD jump sequence data corresponding to the CCD drive timing signal, and then reading the data rhythmically through the jump interval parameter to generate the CCD drive timing signal. The problem of complex implementation schemes in the system also solves the problem of difficulty in upgrading and updating the timing sequence of the CCD drive, and at the same time the implementation cost of the present invention is lower

Method used

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  • A ccd drive sequence processing device
  • A ccd drive sequence processing device
  • A ccd drive sequence processing device

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Embodiment Construction

[0018] Please refer to figure 2 , The present invention provides a CCD drive timing processing device, which can be widely used in various camera equipment including surveillance cameras. In a preferred manner, the device can be realized based on a programmable logic device, and of course it can also be realized by software or hardware. The device includes a timing management module, a timing storage module and a timing output module. In a preferred manner, the sequential storage module can be realized by using RAM or ROM. Taking RAM as an example, the timing management module can update the CCD driver timing table delivered by the developer to the RAM, and the entry data in the CCD driver timing table represents the CCD driver timing signal. After the RAM is updated, the timing output module can read data from the CCD driving timing table and then output the corresponding CCD driving timing signal to drive the CCD device to work.

[0019] Please refer to image 3 , it is...

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Abstract

The invention provides a charge coupled device (CCD) driving schedule processing device. The CCD driving schedule processing device comprises a timing sequence management module, a timing sequence storage module and a timing sequence output module, wherein the timing sequence storage module is used for storing a CCD driving schedule scale. The CCD driving schedule scale comprises a plurality of data lines, wherein each data line comprises CCD jumping sequential data. The timing sequence output module is connected with the timing sequence storage module and used for reading the CCD jumping sequential data in each data line from the CCD driving schedule scale of the memory module, and corresponding CCD driving schedule signals output by the CCD jumping sequential data are transmitted to a CCD device. The CCD driving schedule processing device not only solves the complicated problems of implementation scheme in the prior art, but also solves the problems that the CCD driving schedule updates and renews difficultly, and meanwhile implementation cost is low.

Description

technical field [0001] The invention relates to imaging technology, in particular to a CCD driving timing processing device. Background technique [0002] For the imaging device CCD of the camera, its work requires a corresponding driving sequence. Using FPGA can easily generate CCD driving timing. In the current prior art, a counter is usually used to control the signal edge change of the CCD driving timing. [0003] Please refer to figure 1 , which shows part of the screenshots of the CCD drive timing of the model ICX625AQA sold by Sony. Among them, the "VΦ1" signal "has 9 rising edges + 9 falling edges" in the counting interval from "0 to 6123" (only up to 4865). Generally, the following logic is used to implement: [0004] If (counter value=count value 1)||(counter value=count value 2)||...||((counter value=count value 9)), then the "VΦ1" signal rises to a high level; [0005] If (counter value=count value 1')||(counter value=count value 2')||...||((counter value=c...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04N5/372
Inventor 羊海龙刘强
Owner ZHEJIANG UNIVIEW TECH CO LTD
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