Data processing method and data processing device

A data processing and data technology, applied in the field of communication, can solve problems affecting FPGA processing performance, achieve the effect of reducing the use of memory resources, improving processing efficiency, and improving processing performance

Active Publication Date: 2013-06-19
ZTE CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The present invention provides a data processing method and device to at least solve the problem in the prior art that the processing performance of the FPGA is affected due to the limited memory resources of the FPGA itself

Method used

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  • Data processing method and data processing device
  • Data processing method and data processing device
  • Data processing method and data processing device

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Embodiment 1

[0030] Such as figure 1 As shown, the present invention provides a preferred data processing device 100, which includes: a conversion unit 102, which is used to convert a plurality of serially input data into multiple parallel input data through a multi-way delay shift register ; The data selection switch 104 is used to select data to be processed from multiple channels of parallel input data; the processing unit 106 is used to perform calculation processing on the selected data to be processed.

[0031] In the above-mentioned preferred embodiment, by converting the serial input data into parallel input data through the delay shift register, the serial data is delayed and output through the delay shift register, thereby realizing the need not to use a special memory unit To save the data to be calculated, the purpose of reducing the use of FPGA memory resources is achieved, and the processing performance of the FPGA is improved; at the same time, the data to be processed is se...

Embodiment 2

[0041] based on Figure 1-4 As shown in the preferred data processing device, the present invention also provides a preferred data processing method, such as Figure 5 As shown, the specific steps of the method include:

[0042] S502: Convert multiple serially input data into multiple parallel input data through multiple delay shift registers;

[0043] S504: Select the data to be processed from multiple parallel input data through the data selection switch;

[0044] S506: Perform calculation processing on the selected data to be processed.

[0045] In the above-mentioned preferred embodiment, by converting the serial input data into parallel input data through the delay shift register, the serial data is delayed and output through the delay shift register, thereby realizing the need not to use a special memory unit To save the data to be calculated, the purpose of reducing the use of FPGA memory resources is achieved, and the processing performance of the FPGA is improved; ...

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Abstract

The invention discloses a data processing method and a data processing device. The data processing method comprises a plurality of data which are input in a serial mode is converted into multiple paths of parallel input data through a multi-path time delayed shifting resister, data which need to be processed are selected from the multiple paths of parallel input data through a data selection switch, and operation processing is conducted to the selected data which need to be processed. The data processing method and the data processing device resolve the problem that in the prior art the processing performance of a field programmable gate array (FPGA) is influenced due to the fact that the FPGA is limited in self internal storage resources, and thus the effects that the use of the internal storage resources of the FPGA is reduced and the processing performance of the FPGA is improved are achieved.

Description

technical field [0001] The present invention relates to the communication field, in particular, to a method and data processing method and device. Background technique [0002] FPGA (Field Programmable Gate Array, Field Programmable Gate Array) has been widely used in large data processing (such as wireless baseband data processing) due to its advantages of high integration, high reliability and strong real-time performance. However, FPGA multiplier resources, memory resources, and logic unit resources are very limited. Especially in the process of large-scale baseband data processing, it is often necessary to use a large number of FPGA resources for data multiplication and addition processing. The FPGA resources here mainly refer to It is the memory resource of FPGA, that is, RAM resource. Using too much memory resource will inevitably affect the speed and scale of baseband data processed by FPGA system. Therefore, how to reduce the use of FPGA memory resources and expand t...

Claims

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Application Information

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IPC IPC(8): G06F13/16
Inventor 陆海涛
Owner ZTE CORP
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