Low density parity check (LDPC) decoder and implementation method thereof

A decoder and codeword technology, applied in the direction of using block codes for error correction/detection, applying multi-bit parity bit error detection coding, data representation error detection/correction, etc., can solve the problem of wasting chip resources in storage space, Large storage space, many computing units, etc., to achieve the effect of saving chip resources, reducing storage space, and reducing computing units

Active Publication Date: 2013-06-19
LEADCORE TECH
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0045] However, the above-mentioned traditional LDPC decoding algorithm has the following disadvantages: (1) 108 blocks of RAM are required to store the calculation results of row matrix and column matrix, and the required storage space is relatively large; (2) because it adopts a fully parallel method, Therefore, 18 computing units of CNU (check node) nodes and 36 computing units of VNU (variable node) nodes are required, and many computing units are used.
[0046] To sum up, it can be seen that the traditional LDPC decoding algorithm in the prior art has the problem of requiring a large storage space and wasting chip resources. Therefore, it is necessary to propose improved technical means to solve this problem.

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  • Low density parity check (LDPC) decoder and implementation method thereof
  • Low density parity check (LDPC) decoder and implementation method thereof
  • Low density parity check (LDPC) decoder and implementation method thereof

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Embodiment Construction

[0083] The implementation of the present invention is described below through specific examples and in conjunction with the accompanying drawings, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific examples, and various modifications and changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0084] figure 1 It is a schematic structural diagram of an LDPC decoder of the present invention. Such as figure 1 As shown, an LDPC decoder of the present invention at least includes an input buffer unit 11 , a state control and address generation module 12 , a check node processing module 13 , a variable node processing module 14 and a decision code word storage unit 15 .

[0085] Where...

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Abstract

The invention discloses a low density parity check (LDPC) decoder and an implementation method thereof. The LDPC decoder comprises an input buffer cell, a state control and address generation module, a check node processing module, a variable node processing module and a decision codon storage unit. The input buffer cell comprises an H matrix array unit, a V matrix array unit and an initial information storage unit. Storage of results of row matrix and column matrix is carried out on only 57 ransom access memory (RAM), the number of the RAM is reduced by nearly 50%, and storage space in an implementation process of the LDPC decoder is reduced. At the same time, check node operation is carried out on an arithmetic unit of 5 CNU nodes, variable node operation is carried out on an arithmetic unit of 9 VNU nodes, a needed arithmetic unit in the implementation process of the LDPC decoder is reduced, and the goal of saving chip resources is achieved.

Description

technical field [0001] The invention relates to an LDPC decoder and a realization method thereof, in particular to an LDPC decoder conforming to the CMMB standard and a realization method thereof. Background technique [0002] In modern communication systems, error correction codes are an important means to improve channel transmission reliability and power utilization. LDPC codes (Low Density Parity Check Code, Low Density Parity Check Code) are currently a type of error correction codes that are closest to Shannon's limit. , has been widely used in deep space communication, optical fiber communication, satellite digital video and audio broadcasting and other fields. [0003] In the China Mobile Multimedia Broadcasting Digital System (CMMB, china mobile multimedia broadcasting), RS codes (Reed-solomon codes, Reed-solomon codes) and LDPC codes are concatenated as channel error correction codes. The code length is required to be 9216bit, two code rates of 1 / 2 and 3 / 4 are sup...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/11
Inventor 雷海燕
Owner LEADCORE TECH
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