Compressed data output method for DRAM repair test

Abstract

The invention relates to a compressed data output method for DRAM (dynamic random access memory) repair test. The method comprises the following steps: step 1, reading the value of a 32-bit cell; step 2, judging whether fail exists in the cell through an internal algorithm of a chip; step 3, carrying out calculation of 'and' to the result value of the 32-bit cell inside the chip; step 4, outputting the unique final result value of the 32-bit cell; step 5, after obtaining the result of the 32-bit cell through a testing machine, if the result is '0', a broken bit line CSL exists, then running a processing program to replace the broken bit line CSL with the redundant bit line CSL, and if the result is '1', a broken bit line CSL does not exist. The provided compressed data output method for DRAM repair test shortens the testing time and reduces the testing cost.

Description

technical field [0001] The invention belongs to the field of chip design and relates to a data compression output method for DRAM repair test. Background technique [0002] The most basic unit of DRAM is composed of tens of thousands of cell units (each unit is called a bit), and currently there is no process that can guarantee that all cell units are correct, so once it is found in the front-end test There is a problem with a certain unit, we use redundant units to repair the broken unit; [0003] see figure 1 , when the memory is read and written, the word line WL and bit line CSL will be activated, and the corresponding cell unit will be activated; the intersection of each bit line CSL and word line WL corresponds to 8 cell units ;Taking the DDR2X16 chip as an example, each reading and writing is 64 bits, you need to activate 1 WL and 8 CSLs, a total of 8 intersections, corresponding to 64 cell units; [0004] see figure 2 , the test result information of each cell n...

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Problems solved by technology

[0005] In this way, each chip needs to be connected to 16 IO channels, and 4 cycles can meet our need to read 64 bits; the IO channels that the machine can provide are limited. Take Advantest T5377 as an example, it has 1280 IO channels, if each chip needs to be connected to 16 IO channels, only 80 chips can be tested at the same time; and this number of simultaneous tests is far from meeting our mass production needs, and the cost will also vary depending on the complexity of the process increase, the reading time is relatively long

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