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Composite substrate with isolation layer and manufacturing method thereof

A composite substrate and manufacturing method technology, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of difficulty in forming lattice structures, inability to form lattice structures, and growing GaN semiconductor epitaxial layers, etc. performance, avoid dislocation defect areas, and reduce the effect of manufacturing costs

Active Publication Date: 2016-03-30
INST OF PHYSICS - CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the isolation layer is very thin, it is difficult to form a complete lattice structure, and it is usually amorphous, so the lattice quality of the subsequently grown semiconductor layer is difficult to guarantee
For example, if a silicon dioxide spacer and a GaN semiconductor layer are grown on a sapphire substrate, since the silicon dioxide spacer is an amorphous structure, a complete lattice structure cannot be formed, so it is impossible to directly grow a GaN semiconductor epitaxial layer on the silicon dioxide spacer

Method used

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  • Composite substrate with isolation layer and manufacturing method thereof
  • Composite substrate with isolation layer and manufacturing method thereof
  • Composite substrate with isolation layer and manufacturing method thereof

Examples

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Embodiment 1

[0036] This embodiment provides a method for manufacturing a composite substrate with an isolation layer, the process flow of which is as follows Figure 1-8 shown, including:

[0037] 1) if figure 1 As shown, 300nm thick SiO was deposited on the surface of sapphire substrate 1 by PECVD method 2 The thin film is used as the first sub-isolation layer 2, and then a plurality of openings 21 are formed in the first sub-isolation layer 2 by photolithography and etching processes to expose the surface of the sapphire substrate 1. The plurality of openings 21 form a grating pattern, and the period is 4 microns, the width of the opening 21 is 1 micron;

[0038] 2) if figure 2 As shown, using the MOCVD lateral epitaxial growth technology, the substrate 1 at the opening 21 is used as a seed to prepare a GaN thin film as the seed layer 3, and the seed layer 3 starts epitaxial growth and lateral epitaxial growth from the substrate 1 at the plurality of openings 21, and bonding at th...

Embodiment 2

[0048] This embodiment provides a method for manufacturing a composite substrate with an isolation layer, the process flow of which is as follows Figure 1-8 shown, including:

[0049] 1) if figure 1 As shown, a 300nm thick SiO is formed on the surface of the silicon substrate 1 by PECVD or thermal oxidation. 2 Thin film is used as the first sub-isolating layer 2, and then a plurality of openings 21 are formed in the first sub-isolating layer 2 by photolithography and etching processes, exposing the surface of the silicon substrate 1, and the plurality of openings 21 form a grating pattern, and its period is 4 microns, the width of the opening 21 is 1 micron;

[0050] 2) if figure 2 As shown, using the MOCVD lateral epitaxial growth technology, the substrate 1 at the opening 21 is used as a seed to prepare a GaN thin film as the seed layer 3, and the seed layer 3 starts epitaxial growth and lateral epitaxy from the substrate 1 at the openings 21, and is formed in joining...

Embodiment 3

[0059] This embodiment provides a method for manufacturing a composite substrate with an isolation layer, the process flow of which is as follows Figure 1-8 shown, including:

[0060] 1) if figure 1 As shown, a metal molybdenum film with a thickness of 300 nm is formed on the surface of the sapphire substrate 1 by evaporation or sputtering as the first sub-isolation layer 2, and then a plurality of openings are formed in the first sub-isolation layer 2 by photolithography and etching processes 21, exposing the surface of the sapphire substrate 1, a plurality of openings 21 form a grating pattern, the period of which is 4 microns, and the width of the openings 21 is 1 micron;

[0061] 2) if figure 2 As shown, using the MOCVD lateral epitaxial growth technology, the substrate 1 at the opening 21 is used as a seed to prepare a GaN thin film as the seed layer 3, and the seed layer 3 starts epitaxial growth and lateral epitaxy from the substrate 1 at the openings 21, and is fo...

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Abstract

Provided is a manufacturing method of a composite substrate having an isolation layer, the method comprising: forming on a substrate (1) a first sub isolation layer (1) having an opening (21) exposing the substrate (1); utilizing a lateral growth method to form a seed layer (3) made of a semiconductor material thin film on the first sub isolation layer (2) and the substrate (1); selectively etching the seed layer (3), leaving a part of the seed layer (3) as a seed region (31) on the first sub isolation layer (2); forming a second sub isolation layer (201) covering the substrate (1), the first sub isolation layer (2), and the seed region (31); forming an opening in the second sub isolation layer (201), the opening exposing at least a part of the seed region (31); and using at least a part of the seed region (31) as a seed to grow a semiconductor layer (301) on the second sub isolation layer (201) by employing the lateral growth method.

Description

technical field [0001] The invention relates to a substrate for manufacturing semiconductor devices, in particular to a composite substrate with an isolation layer and a manufacturing method thereof. Background technique [0002] In the semiconductor industry, silicon materials are usually used as substrates, and various semiconductor devices are fabricated on silicon substrates by means of doping, photolithography, deposition, etc. The substrates are electrically coupled, resulting in large leakage currents, high power dissipation, and large parasitic capacitances. [0003] In recent years, a new semiconductor device substrate - silicon on insulator wafer (SOI, Silicon On Insulator) has been developed. Semiconductor devices are formed in the top layer of single crystal silicon. SOI uses a silicon oxide insulating layer to isolate the electrical coupling between the semiconductor device on the top layer and the underlying substrate. SOI-based integrated circuits have a se...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/762H01L21/02H01L29/06
CPCH01L29/78603H01L29/78657H01L29/78681
Inventor 陈弘贾海强江洋王文新马紫光王禄李卫
Owner INST OF PHYSICS - CHINESE ACAD OF SCI