Method and system for reducing power consumption of multi-thread program

Abstract

The invention discloses a method and a system for reducing power consumption of a multi-thread program. The method comprises the steps as follows: when one thread arrives the first barrier, the address of the barrier and the time that the last thread leaves the barrier are recorded in a barrier interval time predicting table; when the last thread leaves the barrier i+1, the time that the last thread leaves the barrier i is subtracted from the time at this moment, so that the interval time of the barrier i is obtained; the address and the interval time of the barrier i are written into the barrier interval time predicting table; when threads arrive the same barrier again, the computation time is subtracted from the interval time read out from the barrier interval time predicting table adopted by the thread arriving a barrier synchronization point first, the busy waiting time of the thread is predicted, and the thread chooses to enter an appropriate low power consumption mode; when the predicted interval time of the barrier is coming, the thread arriving the barrier synchronization point first is restored into a normal power consumption mode, and the barrier interval time predicting table is updated, so that the power consumption of the whole processor is reduced.

Description

technical field [0001] The invention relates to the technical field of reducing power consumption of multi-threaded programs on a multi-core processor, in particular to reducing power consumption overhead caused by a barrier synchronization mechanism of multi-threaded programs. Background technique [0002] As the chip integrates more and more transistors, the design of single-core high-performance processors becomes more and more complicated and difficult to verify, and the design of on-chip multi-core processors CMPs (Chip multi processors) composed of several simple processor cores It is an efficient and simple method. CMPs are a trend in high-performance processor design. CMPs exploit coarser-grained parallelism (thread- or process-level) of programs than traditional instruction-level parallelism during program compilation or runtime. [0003] Reducing power consumption has become a very important goal in the design of high-performance processors. High power consumpti...

AI Technical Summary

Problems solved by technology

It can be seen that the busy waiting operation performed by the thread that reaches the synchronization point first, except that the last iteration cycle detects that the flag bit is flipped, the previous iteration cycles are all invalid operations, resulting in power consumption loss

[0006] Many commercial processors provide a variety of low-power modes, each of which achieves a different degree of power reduction, but produces a corresponding transition time

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